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e9b03ef213
STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-5-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
17 lines
460 B
Plaintext
17 lines
460 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp233.dtsi"
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&rifsc {
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vdec: vdec@480d0000 {
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compatible = "st,stm32mp25-vdec";
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reg = <0x480d0000 0x3c8>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc CK_BUS_VDEC>;
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access-controllers = <&rifsc 89>;
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};
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};
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