mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
e9b03ef213
STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-5-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
95 lines
2.2 KiB
Plaintext
95 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
|
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
|
*/
|
|
#include "stm32mp231.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a35";
|
|
reg = <1>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
power-domains = <&cpu1_pd>;
|
|
power-domain-names = "psci";
|
|
};
|
|
};
|
|
|
|
arm-pmu {
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>;
|
|
};
|
|
|
|
psci {
|
|
cpu1_pd: power-domain-cpu1 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|
|
|
|
&optee {
|
|
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
&rifsc {
|
|
ethernet2: ethernet@482d0000 {
|
|
compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
|
|
reg = <0x482d0000 0x4000>;
|
|
reg-names = "stmmaceth";
|
|
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clock-names = "stmmaceth",
|
|
"mac-clk-tx",
|
|
"mac-clk-rx",
|
|
"ptp_ref",
|
|
"ethstp",
|
|
"eth-ck";
|
|
clocks = <&rcc CK_ETH2_MAC>,
|
|
<&rcc CK_ETH2_TX>,
|
|
<&rcc CK_ETH2_RX>,
|
|
<&rcc CK_KER_ETH2PTP>,
|
|
<&rcc CK_ETH2_STP>,
|
|
<&rcc CK_KER_ETH2>;
|
|
snps,axi-config = <&stmmac_axi_config_2>;
|
|
snps,mixed-burst;
|
|
snps,mtl-rx-config = <&mtl_rx_setup_2>;
|
|
snps,mtl-tx-config = <&mtl_tx_setup_2>;
|
|
snps,pbl = <2>;
|
|
snps,tso;
|
|
st,syscon = <&syscfg 0x3400>;
|
|
access-controllers = <&rifsc 61>;
|
|
status = "disabled";
|
|
|
|
mtl_rx_setup_2: rx-queues-config {
|
|
snps,rx-queues-to-use = <2>;
|
|
queue0 {};
|
|
queue1 {};
|
|
};
|
|
|
|
mtl_tx_setup_2: tx-queues-config {
|
|
snps,tx-queues-to-use = <4>;
|
|
queue0 {};
|
|
queue1 {};
|
|
queue2 {};
|
|
queue3 {};
|
|
};
|
|
|
|
stmmac_axi_config_2: stmmac-axi-config {
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
snps,rd_osr_lmt = <0x7>;
|
|
snps,wr_osr_lmt = <0x7>;
|
|
};
|
|
};
|
|
};
|