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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1bc229e9bb
Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit12e14066f4("irqchip/GIC: Add workaround for aliased GIC400") Fixes:7a57b1bb1a("arm64: dts: st: introduce stm32mp21 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-5-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
129 lines
2.8 KiB
Plaintext
129 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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reg = <0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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arm_wdt: watchdog {
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compatible = "arm,smc-wdt";
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arm,smc-id = <0xbc000000>;
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status = "disabled";
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};
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ck_flexgen_08: clock-64000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <64000000>;
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};
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ck_flexgen_51: clock-200000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi: scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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arm,no-tick-in-suspend;
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x0 0x80000000>;
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dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>;
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <2>;
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rifsc: bus@42080000 {
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compatible = "simple-bus";
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reg = <0x42080000 0x0 0x1000>;
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ranges;
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dma-ranges;
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#address-cells = <1>;
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#size-cells = <2>;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x0 0x400>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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status = "disabled";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp21-syscfg", "syscon";
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reg = <0x44230000 0x0 0x10000>;
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};
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intc: interrupt-controller@4ac10000 {
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compatible = "arm,gic-400";
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reg = <0x4ac10000 0x0 0x1000>,
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<0x4ac20000 0x0 0x20000>,
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<0x4ac40000 0x0 0x20000>,
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<0x4ac60000 0x0 0x20000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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};
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};
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