mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 14:13:39 +00:00
af9feb0b85
For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL almost coincide and cannot be adjusted by HDMI registrer, resulting in poor compatibility of DDC communication. An improvement of the compatibility of DDC can be done by increasing the driver strength of SCL and decreasing the driver strength of SDA to increase the slope of the falling edge. It should be noted that the maximum driving strength of hdmim0_tx1_scl is only 3, which is different from that of the other IOs. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250522020537.1884771-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
518 lines
9.7 KiB
Plaintext
518 lines
9.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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/*
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* This file is auto generated by pin2dts tool, please keep these code
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* by adding changes at end of this file.
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*/
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&pinctrl {
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clk32k {
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/omit-if-no-ref/
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clk32k_out1: clk32k-out1 {
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rockchip,pins =
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/* clk32k_out1 */
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<2 RK_PC5 1 &pcfg_pull_none>;
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};
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};
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eth0 {
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/omit-if-no-ref/
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eth0_pins: eth0-pins {
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rockchip,pins =
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/* eth0_refclko_25m */
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<2 RK_PC3 1 &pcfg_pull_none>;
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};
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};
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fspi {
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/omit-if-no-ref/
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fspim1_pins: fspim1-pins {
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rockchip,pins =
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/* fspi_clk_m1 */
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<2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
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/* fspi_cs0n_m1 */
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<2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
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/* fspi_d0_m1 */
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<2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
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/* fspi_d1_m1 */
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<2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
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/* fspi_d2_m1 */
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<2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
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/* fspi_d3_m1 */
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<2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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fspim1_cs1: fspim1-cs1 {
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rockchip,pins =
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/* fspi_cs1n_m1 */
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<2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
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};
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};
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gmac0 {
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/omit-if-no-ref/
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gmac0_miim: gmac0-miim {
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rockchip,pins =
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/* gmac0_mdc */
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<4 RK_PC4 1 &pcfg_pull_none>,
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/* gmac0_mdio */
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<4 RK_PC5 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_clkinout: gmac0-clkinout {
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rockchip,pins =
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/* gmac0_mclkinout */
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<4 RK_PC3 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_rx_bus2: gmac0-rx-bus2 {
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rockchip,pins =
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/* gmac0_rxd0 */
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<2 RK_PC1 1 &pcfg_pull_none>,
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/* gmac0_rxd1 */
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<2 RK_PC2 1 &pcfg_pull_none>,
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/* gmac0_rxdv_crs */
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<4 RK_PC2 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_tx_bus2: gmac0-tx-bus2 {
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rockchip,pins =
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/* gmac0_txd0 */
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<2 RK_PB6 1 &pcfg_pull_none>,
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/* gmac0_txd1 */
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<2 RK_PB7 1 &pcfg_pull_none>,
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/* gmac0_txen */
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<2 RK_PC0 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_rgmii_clk: gmac0-rgmii-clk {
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rockchip,pins =
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/* gmac0_rxclk */
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<2 RK_PB0 1 &pcfg_pull_none>,
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/* gmac0_txclk */
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<2 RK_PB3 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_rgmii_bus: gmac0-rgmii-bus {
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rockchip,pins =
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/* gmac0_rxd2 */
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<2 RK_PA6 1 &pcfg_pull_none>,
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/* gmac0_rxd3 */
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<2 RK_PA7 1 &pcfg_pull_none>,
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/* gmac0_txd2 */
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<2 RK_PB1 1 &pcfg_pull_none>,
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/* gmac0_txd3 */
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<2 RK_PB2 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_ppsclk: gmac0-ppsclk {
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rockchip,pins =
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/* gmac0_ppsclk */
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<2 RK_PC4 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_ppstring: gmac0-ppstring {
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rockchip,pins =
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/* gmac0_ppstring */
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<2 RK_PB5 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_ptp_refclk: gmac0-ptp-refclk {
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rockchip,pins =
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/* gmac0_ptp_refclk */
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<2 RK_PB4 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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gmac0_txer: gmac0-txer {
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rockchip,pins =
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/* gmac0_txer */
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<4 RK_PC6 1 &pcfg_pull_none>;
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};
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};
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hdmi {
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/omit-if-no-ref/
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hdmim0_tx1_cec: hdmim0-tx1-cec {
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rockchip,pins =
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/* hdmim0_tx1_cec */
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<2 RK_PC4 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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hdmim0_tx1_scl: hdmim0-tx1-scl {
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rockchip,pins =
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/* hdmim0_tx1_scl */
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<2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
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};
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/omit-if-no-ref/
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hdmim0_tx1_sda: hdmim0-tx1-sda {
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rockchip,pins =
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/* hdmim0_tx1_sda */
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<2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
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};
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};
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i2c0 {
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/omit-if-no-ref/
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i2c0m1_xfer: i2c0m1-xfer {
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rockchip,pins =
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/* i2c0_scl_m1 */
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<4 RK_PC5 9 &pcfg_pull_none_smt>,
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/* i2c0_sda_m1 */
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<4 RK_PC6 9 &pcfg_pull_none_smt>;
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};
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};
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i2c2 {
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/omit-if-no-ref/
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins =
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/* i2c2_scl_m1 */
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<2 RK_PC1 9 &pcfg_pull_none_smt>,
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/* i2c2_sda_m1 */
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<2 RK_PC0 9 &pcfg_pull_none_smt>;
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};
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};
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i2c3 {
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/omit-if-no-ref/
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i2c3m3_xfer: i2c3m3-xfer {
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rockchip,pins =
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/* i2c3_scl_m3 */
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<2 RK_PB2 9 &pcfg_pull_none_smt>,
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/* i2c3_sda_m3 */
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<2 RK_PB3 9 &pcfg_pull_none_smt>;
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};
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};
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i2c4 {
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/omit-if-no-ref/
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i2c4m1_xfer: i2c4m1-xfer {
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rockchip,pins =
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/* i2c4_scl_m1 */
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<2 RK_PB5 9 &pcfg_pull_none_smt>,
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/* i2c4_sda_m1 */
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<2 RK_PB4 9 &pcfg_pull_none_smt>;
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};
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};
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i2c5 {
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/omit-if-no-ref/
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i2c5m4_xfer: i2c5m4-xfer {
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rockchip,pins =
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/* i2c5_scl_m4 */
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<2 RK_PB6 9 &pcfg_pull_none_smt>,
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/* i2c5_sda_m4 */
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<2 RK_PB7 9 &pcfg_pull_none_smt>;
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};
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};
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i2c6 {
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/omit-if-no-ref/
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i2c6m2_xfer: i2c6m2-xfer {
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rockchip,pins =
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/* i2c6_scl_m2 */
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<2 RK_PC3 9 &pcfg_pull_none_smt>,
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/* i2c6_sda_m2 */
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<2 RK_PC2 9 &pcfg_pull_none_smt>;
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};
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};
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i2c7 {
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/omit-if-no-ref/
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i2c7m1_xfer: i2c7m1-xfer {
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rockchip,pins =
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/* i2c7_scl_m1 */
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<4 RK_PC3 9 &pcfg_pull_none_smt>,
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/* i2c7_sda_m1 */
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<4 RK_PC4 9 &pcfg_pull_none_smt>;
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};
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};
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i2c8 {
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/omit-if-no-ref/
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i2c8m1_xfer: i2c8m1-xfer {
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rockchip,pins =
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/* i2c8_scl_m1 */
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<2 RK_PB0 9 &pcfg_pull_none_smt>,
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/* i2c8_sda_m1 */
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<2 RK_PB1 9 &pcfg_pull_none_smt>;
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};
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};
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i2s2 {
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/omit-if-no-ref/
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i2s2m0_lrck: i2s2m0-lrck {
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rockchip,pins =
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/* i2s2m0_lrck */
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<2 RK_PC0 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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i2s2m0_mclk: i2s2m0-mclk {
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rockchip,pins =
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/* i2s2m0_mclk */
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<2 RK_PB6 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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i2s2m0_sclk: i2s2m0-sclk {
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rockchip,pins =
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/* i2s2m0_sclk */
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<2 RK_PB7 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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i2s2m0_sdi: i2s2m0-sdi {
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rockchip,pins =
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/* i2s2m0_sdi */
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<2 RK_PC3 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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i2s2m0_sdo: i2s2m0-sdo {
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rockchip,pins =
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/* i2s2m0_sdo */
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<4 RK_PC3 2 &pcfg_pull_none>;
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};
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};
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pwm2 {
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/omit-if-no-ref/
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pwm2m2_pins: pwm2m2-pins {
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rockchip,pins =
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/* pwm2_m2 */
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<4 RK_PC2 11 &pcfg_pull_none>;
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};
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};
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pwm4 {
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/omit-if-no-ref/
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pwm4m1_pins: pwm4m1-pins {
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rockchip,pins =
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/* pwm4_m1 */
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<4 RK_PC3 11 &pcfg_pull_none>;
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};
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};
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pwm5 {
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/omit-if-no-ref/
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pwm5m2_pins: pwm5m2-pins {
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rockchip,pins =
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/* pwm5_m2 */
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<4 RK_PC4 11 &pcfg_pull_none>;
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};
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};
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pwm6 {
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/omit-if-no-ref/
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pwm6m2_pins: pwm6m2-pins {
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rockchip,pins =
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/* pwm6_m2 */
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<4 RK_PC5 11 &pcfg_pull_none>;
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};
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};
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pwm7 {
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/omit-if-no-ref/
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pwm7m3_pins: pwm7m3-pins {
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rockchip,pins =
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/* pwm7_ir_m3 */
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<4 RK_PC6 11 &pcfg_pull_none>;
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};
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};
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sdio {
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/omit-if-no-ref/
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sdiom0_pins: sdiom0-pins {
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rockchip,pins =
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/* sdio_clk_m0 */
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<2 RK_PB3 2 &pcfg_pull_none>,
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/* sdio_cmd_m0 */
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<2 RK_PB2 2 &pcfg_pull_none>,
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/* sdio_d0_m0 */
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<2 RK_PA6 2 &pcfg_pull_none>,
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/* sdio_d1_m0 */
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<2 RK_PA7 2 &pcfg_pull_none>,
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/* sdio_d2_m0 */
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<2 RK_PB0 2 &pcfg_pull_none>,
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/* sdio_d3_m0 */
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<2 RK_PB1 2 &pcfg_pull_none>;
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};
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};
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spi1 {
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/omit-if-no-ref/
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spi1m0_pins: spi1m0-pins {
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rockchip,pins =
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/* spi1_clk_m0 */
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<2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
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/* spi1_miso_m0 */
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<2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
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/* spi1_mosi_m0 */
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<2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
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};
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/omit-if-no-ref/
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spi1m0_cs0: spi1m0-cs0 {
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rockchip,pins =
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/* spi1_cs0_m0 */
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<2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
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};
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/omit-if-no-ref/
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spi1m0_cs1: spi1m0-cs1 {
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rockchip,pins =
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/* spi1_cs1_m0 */
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<2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
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};
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};
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spi3 {
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/omit-if-no-ref/
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spi3m0_pins: spi3m0-pins {
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rockchip,pins =
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/* spi3_clk_m0 */
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<4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
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/* spi3_miso_m0 */
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<4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
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/* spi3_mosi_m0 */
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<4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
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};
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/omit-if-no-ref/
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spi3m0_cs0: spi3m0-cs0 {
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rockchip,pins =
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/* spi3_cs0_m0 */
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<4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
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};
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/omit-if-no-ref/
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spi3m0_cs1: spi3m0-cs1 {
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rockchip,pins =
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/* spi3_cs1_m0 */
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<4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
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};
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};
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uart1 {
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/omit-if-no-ref/
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uart1m0_xfer: uart1m0-xfer {
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rockchip,pins =
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/* uart1_rx_m0 */
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<2 RK_PB6 10 &pcfg_pull_up>,
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/* uart1_tx_m0 */
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<2 RK_PB7 10 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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uart1m0_ctsn: uart1m0-ctsn {
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rockchip,pins =
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/* uart1m0_ctsn */
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<2 RK_PC1 10 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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uart1m0_rtsn: uart1m0-rtsn {
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rockchip,pins =
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/* uart1m0_rtsn */
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<2 RK_PC0 10 &pcfg_pull_none>;
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};
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};
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uart6 {
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/omit-if-no-ref/
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uart6m0_xfer: uart6m0-xfer {
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rockchip,pins =
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/* uart6_rx_m0 */
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<2 RK_PA6 10 &pcfg_pull_up>,
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/* uart6_tx_m0 */
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<2 RK_PA7 10 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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uart6m0_ctsn: uart6m0-ctsn {
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rockchip,pins =
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/* uart6m0_ctsn */
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<2 RK_PB1 10 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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uart6m0_rtsn: uart6m0-rtsn {
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rockchip,pins =
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/* uart6m0_rtsn */
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<2 RK_PB0 10 &pcfg_pull_none>;
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};
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};
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uart7 {
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/omit-if-no-ref/
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uart7m0_xfer: uart7m0-xfer {
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rockchip,pins =
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/* uart7_rx_m0 */
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<2 RK_PB4 10 &pcfg_pull_up>,
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/* uart7_tx_m0 */
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<2 RK_PB5 10 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
|
|
uart7m0_ctsn: uart7m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart7m0_ctsn */
|
|
<4 RK_PC6 10 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart7m0_rtsn: uart7m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart7m0_rtsn */
|
|
<4 RK_PC2 10 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart9 {
|
|
/omit-if-no-ref/
|
|
uart9m0_xfer: uart9m0-xfer {
|
|
rockchip,pins =
|
|
/* uart9_rx_m0 */
|
|
<2 RK_PC4 10 &pcfg_pull_up>,
|
|
/* uart9_tx_m0 */
|
|
<2 RK_PC2 10 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart9m0_ctsn: uart9m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart9m0_ctsn */
|
|
<4 RK_PC5 10 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart9m0_rtsn: uart9m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart9m0_rtsn */
|
|
<4 RK_PC4 10 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|