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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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73d6eb7e77
Add device tree overlay for the WolfVision PF5 Visualizer display. Since there shall be additional variants of the WolfVision PF5 display in future, move common definitions to a device tree include file. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20240412-feature-wolfvision-pf5-display-v1-1-f032f32dba1a@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
122 lines
2.8 KiB
Plaintext
122 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Device tree overlay base for the WolfVision PF5 displays.
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*
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* Copyright (C) 2024 WolfVision GmbH.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,vop2.h>
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&{/} {
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display_backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <0 255>;
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default-brightness-level = <255>;
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num-interpolated-steps = <255>;
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power-supply = <&vcc3v3_sd>;
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pwms = <&pwm10 0 1000000 0>;
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};
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display_spi: spi {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
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miso-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
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mosi-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
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num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_spi>;
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sck-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
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st7789: panel@0 {
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compatible = "sitronix,st7789v";
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reg = <0>;
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assigned-clocks = <&cru PLL_VPLL>;
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assigned-clock-rates = <700000000>;
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backlight = <&display_backlight>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc_clock &lcdc_data18 &lcd_rstn>;
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power-supply = <&vcc3v3_sw>;
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reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <100000>;
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port {
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panel_in_vp2: endpoint {
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remote-endpoint = <&vp2_out_rgb>;
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};
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};
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};
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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st1624: touchscreen@55 {
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compatible = "sitronix,st1624", "sitronix,st1633";
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reg = <0x55>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
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gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&touch_int &touch_rstn>;
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wakeup-source;
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};
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};
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&pinctrl {
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display: display-pinctrl {
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lcd_rstn: lcd-rstn-pinctrl {
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rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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lcd_spi: lcd-spi-pinctrl {
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rockchip,pins =
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/* lcd_sdo */
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<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,
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/* lcd_csn */
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<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
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/* lcd_scl */
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<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
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/* lcd_sdi */
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<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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touchscreen: touchscreen-pinctrl {
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touch_int: touch-int-pinctrl {
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rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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touch_rstn: touch-rstn-pinctrl {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm10 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm10m1_pins>;
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status = "okay";
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};
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&vp2 {
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#address-cells = <1>;
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#size-cells = <0>;
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vp2_out_rgb: endpoint@ROCKCHIP_VOP2_EP_RGB0 {
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reg = <ROCKCHIP_VOP2_EP_RGB0>;
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remote-endpoint = <&panel_in_vp2>;
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};
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};
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