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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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68f03b6e0d
Add SD/OE pin properties to the devicetree so that Linux can configure the pin without relying on the OTP. This matches the register configuration reported by Geert [1], as well as my inspection of the schematic (which shows the SD/OE pin permanently tied high). [1] https://lore.kernel.org/linux-clk/CAMuHMdW9LMuQLuPEF-Fcs1E6Q7dDzY17VZqu4awKDj5WSTRt=A@mail.gmail.com/ Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240926180903.479895-2-sean.anderson@linux.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
88 lines
1.8 KiB
Plaintext
88 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Salvator-X 2nd version board
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*
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* Copyright (C) 2015-2017 Renesas Electronics Corp.
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*/
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#include "salvator-common.dtsi"
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/ {
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model = "Renesas Salvator-X 2nd version board";
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compatible = "renesas,salvator-xs";
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};
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&extal_clk {
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clock-frequency = <16640000>;
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};
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&i2c4 {
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clock-frequency = <400000>;
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versaclock6: clock-generator@6a {
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compatible = "idt,5p49v6901";
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reg = <0x6a>;
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#clock-cells = <1>;
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clocks = <&x23_clk>;
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clock-names = "xin";
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idt,shutdown = <0>;
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idt,output-enable-active = <1>;
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};
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};
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#ifdef SOC_HAS_SATA
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&pca9654 {
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pcie-sata-switch-hog {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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output-low; /* enable SATA by default */
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line-name = "PCIE/SATA switch";
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};
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};
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/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
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#endif /* SOC_HAS_SATA */
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#ifdef SOC_HAS_USB2_CH3
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&ehci3 {
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dr_mode = "otg";
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status = "okay";
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};
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&hsusb3 {
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dr_mode = "otg";
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status = "okay";
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};
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&ohci3 {
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dr_mode = "otg";
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status = "okay";
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};
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&pfc {
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/*
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* - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
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* (when SW31 is the default setting on Salvator-XS).
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* - If SW31 is the default setting, you cannot use USB2.0 ch3 on
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* r8a77951 with Salvator-XS.
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* Hence the SW31 setting must be changed like 2) below.
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* 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
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* - Connect GP6_3[01] to ADV7842.
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* 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
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* - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
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* - Connect GP6_{04,21} to ADV7842.
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*/
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usb2_ch3_pins: usb2_ch3 {
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groups = "usb2_ch3";
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function = "usb2_ch3";
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};
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};
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&usb2_phy3 {
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pinctrl-0 = <&usb2_ch3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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#endif /* SOC_HAS_USB2_CH3 */
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