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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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02760e35b5
There are different switches available on both the RZ/G3S SMARC Module and RZ SMARC Carrier II boards. These switches are used to route different SoC signals to different parts available on board. These switches are described in device trees through macros. These macros are set accordingly such that the resulted compiled dtb to describe the on-board switches states. The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches. SCIF1 can be enabled through a device tree overlay. To manage all switches in a unified state and allow users to configure the output device tree, add a file that contains all switch definitions and states. Commit prepares the code to enable SCIF1 on the RZ/G3S overlay. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
385 lines
8.5 KiB
Plaintext
385 lines
8.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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#include "rzg3s-smarc-switches.h"
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/ {
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compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
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aliases {
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i2c1 = &i2c1;
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mmc0 = &sdhi0;
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#if SW_CONFIG3 == SW_OFF
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mmc2 = &sdhi2;
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#else
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ethernet0 = ð0;
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ethernet1 = ð1;
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#endif
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};
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memory@48000000 {
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device_type = "memory";
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/* First 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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vcc_sdhi0: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi0: regulator1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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};
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reg_1p8v: regulator2 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator3 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vcc_sdhi2: regulator4 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI2 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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x3_clk: x3-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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&adc {
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status = "okay";
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};
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#if SW_CONFIG3 == SW_ON
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ð0 {
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pinctrl-0 = <ð0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@7 {
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reg = <7>;
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interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
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rxc-skew-psec = <0>;
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txc-skew-psec = <0>;
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rxdv-skew-psec = <0>;
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txen-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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ð1 {
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pinctrl-0 = <ð1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy1: ethernet-phy@7 {
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reg = <7>;
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interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
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rxc-skew-psec = <0>;
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txc-skew-psec = <0>;
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rxdv-skew-psec = <0>;
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txen-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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#endif
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&extal_clk {
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clock-frequency = <24000000>;
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};
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&i2c1 {
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status = "okay";
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versa3: clock-generator@68 {
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compatible = "renesas,5l35023";
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reg = <0x68>;
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clocks = <&x3_clk>;
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#clock-cells = <1>;
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assigned-clocks = <&versa3 0>,
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<&versa3 1>,
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<&versa3 2>,
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<&versa3 3>,
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<&versa3 4>,
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<&versa3 5>;
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assigned-clock-rates = <24000000>,
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<12288000>,
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<11289600>,
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<25000000>,
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<100000000>,
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<100000000>;
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renesas,settings = [
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80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
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00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
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a0 80 30 30 9c
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];
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};
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};
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#if SW_CONFIG2 == SW_ON
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/* SD0 slot */
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_uhs_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <&vccq_sdhi0>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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max-frequency = <125000000>;
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status = "okay";
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};
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#else
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/* eMMC */
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&sdhi0 {
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pinctrl-0 = <&sdhi0_emmc_pins>;
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pinctrl-1 = <&sdhi0_emmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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max-frequency = <125000000>;
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status = "okay";
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};
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#endif
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#if SW_CONFIG3 == SW_OFF
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&sdhi2 {
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&vcc_sdhi2>;
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bus-width = <4>;
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max-frequency = <50000000>;
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status = "okay";
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};
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#endif
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&pinctrl {
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#if SW_CONFIG3 == SW_ON
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eth0-phy-irq-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
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input;
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line-name = "eth0-phy-irq";
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};
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#endif
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eth0_pins: eth0 {
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txc {
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pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
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power-source = <1800>;
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output-enable;
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input-enable;
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drive-strength-microamp = <5200>;
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};
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tx_ctl {
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pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
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power-source = <1800>;
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output-enable;
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drive-strength-microamp = <5200>;
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};
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mux {
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pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
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<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
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<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
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<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
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<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
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<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
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<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
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<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
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<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
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<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
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<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
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<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
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<RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */
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power-source = <1800>;
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};
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};
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#if SW_CONFIG3 == SW_ON
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eth1-phy-irq-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
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input;
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line-name = "eth1-phy-irq";
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};
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#endif
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eth1_pins: eth1 {
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txc {
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pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
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power-source = <1800>;
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output-enable;
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input-enable;
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drive-strength-microamp = <5200>;
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};
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tx_ctl {
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pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */
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power-source = <1800>;
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output-enable;
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drive-strength-microamp = <5200>;
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};
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mux {
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pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
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<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
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<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
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<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
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<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
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<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
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<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
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<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
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<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
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<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
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<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
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<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
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<RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
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power-source = <1800>;
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};
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};
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sdhi0_pins: sd0 {
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data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <3300>;
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};
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ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <3300>;
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};
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cd {
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pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
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};
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};
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sdhi0_uhs_pins: sd0-uhs {
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data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <1800>;
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};
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ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <1800>;
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};
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cd {
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pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
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};
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};
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sdhi0_emmc_pins: sd0-emmc {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
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"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
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"SD0_CLK", "SD0_CMD", "SD0_RST#";
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power-source = <1800>;
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};
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sdhi2_pins: sd2 {
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data {
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pins = "P11_2", "P11_3", "P12_0", "P12_1";
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input-enable;
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};
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ctrl {
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pins = "P11_1";
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input-enable;
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};
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mux {
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pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
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<RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
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<RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
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<RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
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<RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
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<RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
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<RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&vbattb {
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assigned-clocks = <&vbattb VBATTB_MUX>;
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assigned-clock-parents = <&vbattb VBATTB_XC>;
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quartz-load-femtofarads = <12500>;
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status = "okay";
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};
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&vbattb_xtal {
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clock-frequency = <32768>;
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};
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&wdt0 {
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timeout-sec = <60>;
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status = "okay";
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};
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