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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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20b02acbd8
The Sparrow Hawk board supplies the PCIe controller input clock and PCIe
bus clock from separate outputs of the Renesas 9FGV0441 clock generator.
Describe this split bus configuration in the board DT.
The topology looks as follows:
____________ _____________
| R-Car PCIe | | PCIe device |
| | | |
| PCIe RX<|==================|>PCIe TX |
| PCIe TX<|==================|>PCIe RX |
| | | |
| PCIe CLK<|======.. ..======|>PCIe CLK |
'------------' || || '-------------'
|| ||
____________ || ||
| 9FGV0441 | || ||
| | || ||
| CLK DIF0<|======'' ||
| CLK DIF1<|==========''
| CLK DIF2<|
| CLK DIF3<|
'------------'
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/20250607194541.79176-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
800 lines
15 KiB
Plaintext
800 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
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*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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/*
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* DA7212 Codec settings
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*
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* for Playback
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* > amixer set "Headphone" 40%
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* > amixer set "Headphone" on
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* > amixer set "Mixout Left DAC Left" on
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* > amixer set "Mixout Right DAC Right" on
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* > aplay xxx.wav
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*
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* for Capture (Aux/Mic)
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*
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* on/off (B)
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* CONN3 (HeadSet) ---+----> MSIOF1
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* |
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* CONN4 AUX ---------+ on/off (A)
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*
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* > amixer set "Mixin PGA" on
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* > amixer set "Mixin PGA" 50%
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* > amixer set "ADC" on
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* > amixer set "ADC" 80%
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* > amixer set "Aux" on ^
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* > amixer set "Aux" 80% | (A)
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* > amixer set "Mixin Left Aux Left" on |
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* > amixer set "Mixin Right Aux Right" on v
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* > amixer set "Mic 1" on ^
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* > amixer set "Mic 1" 80% | (B)
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* > amixer set "Mixin Left Mic 1" on |
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* > amixer set "Mixin Right Mic 1" on v
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* > arecord -f cd xxx.wav
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "r8a779g3.dtsi"
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/ {
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model = "Retronix Sparrow Hawk board based on r8a779g3";
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compatible = "retronix,sparrow-hawk", "renesas,r8a779g3",
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"renesas,r8a779g0";
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aliases {
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ethernet0 = &avb0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &hscif0;
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serial1 = &hscif1;
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serial2 = &hscif3;
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spi0 = &rpc;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:921600n8";
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};
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/* Page 31 / FAN */
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fan: pwm-fan {
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pinctrl-0 = <&irq4_pins>;
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pinctrl-names = "default";
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>;
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/*
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* The fan model connected to this device can be selected
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* by user. Set "cooling-levels" DT property to single 255
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* entry to force the fan PWM into constant HIGH, which
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* forces the fan to spin at maximum RPM, thus providing
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* maximum cooling to this device and protection against
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* misconfigured PWM duty cycle to the fan.
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*
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* User has to configure "pwms" and "pulses-per-revolution"
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* DT properties according to fan datasheet first, and then
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* extend "cooling-levels = <0 m n ... 255>" property to
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* achieve proper fan control compatible with fan model
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* installed by user.
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*/
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cooling-levels = <255>;
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pulses-per-revolution = <2>;
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pwms = <&pwm0 0 50000>;
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};
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/*
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* Page 15 / LPDDR5
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*
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* This configuration listed below is for the 8 GiB board variant
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* with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board.
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*
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* A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on
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* the board is automatically handled by the bootloader, which
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* adjusts the correct DRAM size into the memory nodes below.
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*/
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x0 0x80000000>;
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};
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memory@600000000 {
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device_type = "memory";
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reg = <0x6 0x00000000 0x1 0x00000000>;
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};
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/* Page 27 / DSI to Display */
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mini-dp-con {
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compatible = "dp-connector";
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label = "CN6";
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type = "full-size";
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port {
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mini_dp_con_in: endpoint {
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remote-endpoint = <&sn65dsi86_out>;
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};
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};
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};
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/* Page 26 / PCIe.0/1 CLK */
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pcie_refclk: clk-x8 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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reg_1p2v: regulator-1p2v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* Page 27 / DSI to Display */
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sn65dsi86_refclk: clk-x9 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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};
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/* Page 30 / Audio_Codec */
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sound_card: sound {
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compatible = "audio-graph-card2";
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links = <&msiof1_snd>;
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};
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/* Page 17 uSD-Slot */
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vcc_sdhi: regulator-vcc-sdhi {
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compatible = "regulator-gpio";
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regulator-name = "SDHI VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 0>, <1800000 1>;
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};
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};
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&audio_clkin {
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clock-frequency = <24576000>;
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};
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/* Page 22 / Ether_AVB0 */
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&avb0_phy>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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/* AVB0_PHY_INT_V */
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interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
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/* GP7_10/AVB0_RESETN_V */
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <300>;
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};
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};
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};
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/* Page 28 / CANFD_IF */
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&can_clk {
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clock-frequency = <40000000>;
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};
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/* Page 28 / CANFD_IF */
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&canfd {
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pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel3 {
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status = "okay";
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};
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channel4 {
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status = "okay";
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};
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};
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/* Page 27 / DSI to Display */
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&dsi1 {
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status = "okay";
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ports {
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port@1 {
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dsi1_out: endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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/* Page 27 / DSI to Display */
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&du {
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status = "okay";
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extal_clk { /* X3 */
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clock-frequency = <16666666>;
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extalr_clk { /* X2 */
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clock-frequency = <32768>;
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};
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/* Page 26 / 2230 Key M M.2 */
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&gpio4 {
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/* 9FGV0441 nOE inputs 0 and 1 */
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pcie-m2-oe-hog {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-M2";
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};
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/* 9FGV0441 nOE inputs 2 and 3 */
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pcie-usb-oe-hog {
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gpio-hog;
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gpios = <22 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-USB";
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};
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};
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/* Page 23 / DEBUG */
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&hscif0 { /* FTDI ADBUS[3:0] */
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bootph-all;
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status = "okay";
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};
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/* Page 23 / DEBUG */
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&hscif1 { /* FTDI BDBUS[3:0] */
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pinctrl-0 = <&hscif1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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/* Page 24 / UART */
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&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */
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pinctrl-0 = <&hscif3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/* Page 24 / I2C SWITCH */
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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mux@71 {
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compatible = "nxp,pca9544"; /* TCA9544 */
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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vdd-supply = <®_3p3v>;
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i2c0_mux0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 27 / DSI to Display */
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bridge@2c {
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pinctrl-0 = <&irq0_pins>;
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pinctrl-names = "default";
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compatible = "ti,sn65dsi86";
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reg = <0x2c>;
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clocks = <&sn65dsi86_refclk>;
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clock-names = "refclk";
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interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
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enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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vccio-supply = <®_1p8v>;
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vpll-supply = <®_1p8v>;
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vcca-supply = <®_1p2v>;
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vcc-supply = <®_1p2v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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sn65dsi86_in: endpoint {
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remote-endpoint = <&dsi1_out>;
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};
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};
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port@1 {
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reg = <1>;
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sn65dsi86_out: endpoint {
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remote-endpoint = <&mini_dp_con_in>;
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};
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};
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};
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};
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};
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i2c0_mux1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 30 / Audio_Codec */
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codec@1a {
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compatible = "dlg,da7212";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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clocks = <&rcar_sound>;
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clock-names = "mclk";
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VDDA-supply = <®_1p8v>;
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VDDMIC-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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port {
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da7212_endpoint: endpoint {
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bitclock-master;
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frame-master;
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remote-endpoint = <&msiof1_snd_endpoint>;
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};
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};
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};
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};
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i2c0_mux2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 26 / PCIe.0/1 CLK */
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pcie_clk: clk@68 {
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compatible = "renesas,9fgv0441";
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reg = <0x68>;
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clocks = <&pcie_refclk>;
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#clock-cells = <1>;
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};
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};
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i2c0_mux3: i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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/* Page 29 / CSI_IF_CN / CAM_CN0 */
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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/* Page 29 / CSI_IF_CN / CAM_CN1 */
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&i2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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};
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/* Page 31 / IO_CN */
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&i2c3 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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};
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/* Page 31 / IO_CN */
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&i2c4 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-names = "default";
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};
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/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */
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&i2c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c5_pins>;
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pinctrl-names = "default";
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};
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/* Page 17 uSD-Slot */
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&mmc0 {
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pinctrl-0 = <&sd_pins>;
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pinctrl-1 = <&sd_uhs_pins>;
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pinctrl-names = "default", "state_uhs";
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bus-width = <4>;
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cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vcc_sdhi>;
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status = "okay";
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};
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&msiof1 {
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pinctrl-0 = <&msiof1_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* ignore DT warning */
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/delete-property/#address-cells;
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/delete-property/#size-cells;
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msiof1_snd: port {
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msiof1_snd_endpoint: endpoint {
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remote-endpoint = <&da7212_endpoint>;
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};
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};
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};
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/* Page 26 / 2230 Key M M.2 */
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&pcie0_clkref {
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status = "disabled";
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};
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&pciec0 {
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clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
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reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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status = "okay";
|
|
};
|
|
|
|
&pciec0_rp {
|
|
clocks = <&pcie_clk 1>;
|
|
vpcie3v3-supply = <®_3p3v>;
|
|
};
|
|
|
|
/* Page 25 / PCIe to USB */
|
|
&pcie1_clkref {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pciec1 {
|
|
clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
|
|
/* uPD720201 is PCIe Gen2 x1 device */
|
|
num-lanes = <1>;
|
|
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pciec1_rp {
|
|
clocks = <&pcie_clk 3>;
|
|
vpcie3v3-supply = <®_3p3v>;
|
|
};
|
|
|
|
&pfc {
|
|
pinctrl-0 = <&scif_clk_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* Page 22 / Ether_AVB0 */
|
|
avb0_pins: avb0 {
|
|
mux {
|
|
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
|
|
"avb0_txcrefclk";
|
|
function = "avb0";
|
|
};
|
|
|
|
pins-mdio {
|
|
groups = "avb0_mdio";
|
|
drive-strength = <21>;
|
|
};
|
|
|
|
pins-mii {
|
|
groups = "avb0_rgmii";
|
|
drive-strength = <21>;
|
|
};
|
|
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
can_clk_pins: can-clk {
|
|
groups = "can_clk";
|
|
function = "can_clk";
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
canfd3_pins: canfd3 {
|
|
groups = "canfd3_data";
|
|
function = "canfd3";
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
canfd4_pins: canfd4 {
|
|
groups = "canfd4_data";
|
|
function = "canfd4";
|
|
};
|
|
|
|
/* Page 23 / DEBUG */
|
|
hscif0_pins: hscif0 {
|
|
groups = "hscif0_data", "hscif0_ctrl";
|
|
function = "hscif0";
|
|
};
|
|
|
|
/* Page 23 / DEBUG */
|
|
hscif1_pins: hscif1 {
|
|
groups = "hscif1_data_a", "hscif1_ctrl_a";
|
|
function = "hscif1";
|
|
};
|
|
|
|
/* Page 24 / UART */
|
|
hscif3_pins: hscif3 {
|
|
groups = "hscif3_data_a";
|
|
function = "hscif3";
|
|
};
|
|
|
|
/* Page 24 / I2C SWITCH */
|
|
i2c0_pins: i2c0 {
|
|
groups = "i2c0";
|
|
function = "i2c0";
|
|
};
|
|
|
|
/* Page 29 / CSI_IF_CN / CAM_CN0 */
|
|
i2c1_pins: i2c1 {
|
|
groups = "i2c1";
|
|
function = "i2c1";
|
|
};
|
|
|
|
/* Page 29 / CSI_IF_CN / CAM_CN1 */
|
|
i2c2_pins: i2c2 {
|
|
groups = "i2c2";
|
|
function = "i2c2";
|
|
};
|
|
|
|
/* Page 31 / IO_CN */
|
|
i2c3_pins: i2c3 {
|
|
groups = "i2c3";
|
|
function = "i2c3";
|
|
};
|
|
|
|
/* Page 31 / IO_CN */
|
|
i2c4_pins: i2c4 {
|
|
groups = "i2c4";
|
|
function = "i2c4";
|
|
};
|
|
|
|
/* Page 18 / POWER_CORE */
|
|
i2c5_pins: i2c5 {
|
|
groups = "i2c5";
|
|
function = "i2c5";
|
|
};
|
|
|
|
/* Page 27 / DSI to Display */
|
|
irq0_pins: irq0 {
|
|
groups = "intc_ex_irq0_a";
|
|
function = "intc_ex";
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
irq4_pins: irq4 {
|
|
groups = "intc_ex_irq4_b";
|
|
function = "intc_ex";
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
pwm0_pins: pwm0 {
|
|
groups = "pwm0";
|
|
function = "pwm0";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 12 */
|
|
pwm1_pins: pwm1 {
|
|
groups = "pwm1_b";
|
|
function = "pwm1";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 32 */
|
|
pwm6_pins: pwm6 {
|
|
groups = "pwm6";
|
|
function = "pwm6";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 33 */
|
|
pwm7_pins: pwm7 {
|
|
groups = "pwm7";
|
|
function = "pwm7";
|
|
};
|
|
|
|
/* Page 16 / QSPI_FLASH */
|
|
qspi0_pins: qspi0 {
|
|
groups = "qspi0_ctrl", "qspi0_data4";
|
|
function = "qspi0";
|
|
bootph-all;
|
|
};
|
|
|
|
/* Page 6 / SCIF_CLK_SOC_V */
|
|
scif_clk_pins: scif-clk {
|
|
groups = "scif_clk";
|
|
function = "scif_clk";
|
|
};
|
|
|
|
/* Page 17 uSD-Slot */
|
|
sd_pins: sd {
|
|
groups = "mmc_data4", "mmc_ctrl";
|
|
function = "mmc";
|
|
power-source = <3300>;
|
|
};
|
|
|
|
/* Page 17 uSD-Slot */
|
|
sd_uhs_pins: sd-uhs {
|
|
groups = "mmc_data4", "mmc_ctrl";
|
|
function = "mmc";
|
|
power-source = <1800>;
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
msiof1_pins: sound {
|
|
groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd";
|
|
function = "msiof1";
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
sound_clk_pins: sound-clk {
|
|
groups = "audio_clkin", "audio_clkout";
|
|
function = "audio_clk";
|
|
};
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
&pwm0 {
|
|
pinctrl-0 = <&pwm0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 12 */
|
|
&pwm1 {
|
|
pinctrl-0 = <&pwm1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 32 */
|
|
&pwm6 {
|
|
pinctrl-0 = <&pwm6_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 33 */
|
|
&pwm7 {
|
|
pinctrl-0 = <&pwm7_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
&rcar_sound {
|
|
pinctrl-0 = <&sound_clk_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* It is used for ADG output as DA7212_MCLK */
|
|
|
|
/* audio_clkout */
|
|
clock-frequency = <12288000>; /* 48 kHz groups */
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 16 / QSPI_FLASH */
|
|
&rpc {
|
|
pinctrl-0 = <&qspi0_pins>;
|
|
pinctrl-names = "default";
|
|
bootph-all;
|
|
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <40000000>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-tx-bus-width = <4>;
|
|
bootph-all;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
boot@0 {
|
|
reg = <0x0 0x1000000>;
|
|
read-only;
|
|
};
|
|
|
|
user@1000000 {
|
|
reg = <0x1000000 0x2f80000>;
|
|
};
|
|
|
|
env1@3f80000 {
|
|
reg = <0x3f80000 0x40000>;
|
|
};
|
|
|
|
env2@3fc0000 {
|
|
reg = <0x3fc0000 0x40000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rwdt {
|
|
timeout-sec = <60>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 6 / SCIF_CLK_SOC_V */
|
|
&scif_clk { /* X12 */
|
|
clock-frequency = <24000000>;
|
|
};
|