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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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567d37b954
Each kit-level file represents a SOM + baseboard for a specific SoC type and uses specific clocks unique to each SoC. With the exception of one clock, the rest of the clock info was duplicated. There is a generic clock called CPG_AUDIO_CLK_I defined in each of the SoC DTSI files which points to this unique clock. By using that, the clock information for the rcar_sound can be consolidated into the baseboard file and have it reference this generic clock thus removing the duplication from the three variants. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230104141245.8407-4-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
61 lines
1.1 KiB
Plaintext
61 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020, Compass Electronics Group, LLC
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*/
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/dts-v1/;
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#include "r8a774a1.dtsi"
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#include "beacon-renesom-som.dtsi"
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#include "beacon-renesom-baseboard.dtsi"
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/ {
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model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
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compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &iic_pmic;
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serial0 = &scif2;
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serial1 = &hscif0;
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serial2 = &hscif1;
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serial3 = &scif0;
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serial4 = &hscif2;
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serial5 = &scif5;
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ethernet0 = &avb;
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mmc0 = &sdhi3;
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mmc1 = &sdhi0;
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mmc2 = &sdhi2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@600000000 {
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device_type = "memory";
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reg = <0x6 0x00000000 0x0 0x80000000>;
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};
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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<&versaclock5 1>,
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<&x302_clk>,
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<&versaclock5 2>;
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clock-names = "du.0", "du.1", "du.2",
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"dclkin.0", "dclkin.1", "dclkin.2";
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};
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