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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7a242135a4
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: rtd1293-ds418j.dtb: l2-cache: 'cache-level' is a required property rtd1293-ds418j.dtb: l2-cache: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223151.115243-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
68 lines
1.2 KiB
Plaintext
68 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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/*
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* Realtek RTD1395 SoC
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*
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* Copyright (c) 2019 Andreas Färber
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*/
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#include "rtd139x.dtsi"
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/ {
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compatible = "realtek,rtd1395";
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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&arm_pmu {
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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