mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 14:13:39 +00:00
7bd7209e9c
Fix the incorrect IRQ numbers for ready and handover on sa8775p.
The correct values are as follows:
Fatal interrupt - 0
Ready interrupt - 1
Handover interrupt - 2
Stop acknowledge interrupt - 3
Fixes: df54dcb34f ("arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes")
Signed-off-by: Lijuan Gao <lijuan.gao@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250612-correct_interrupt_for_remoteproc-v1-2-490ee6d92a1b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7901 lines
194 KiB
Plaintext
7901 lines
194 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Linaro Limited
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
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#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/firmware/qcom,scm.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&l2_0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
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&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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power-domains = <&cpu_pd1>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&l2_1>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
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&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
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l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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power-domains = <&cpu_pd2>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&l2_2>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
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&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
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l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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power-domains = <&cpu_pd3>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&l2_3>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
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&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
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l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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power-domains = <&cpu_pd4>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&l2_4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
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l2_4: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_1>;
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l3_1: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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power-domains = <&cpu_pd5>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&l2_5>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
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l2_5: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_1>;
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};
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10200>;
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enable-method = "psci";
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power-domains = <&cpu_pd6>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&l2_6>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
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l2_6: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_1>;
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};
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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power-domains = <&cpu_pd7>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&l2_7>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
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l2_7: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_1>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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gold_cpu_sleep_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <549>;
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exit-latency-us = <901>;
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min-residency-us = <1774>;
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local-timer-stop;
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};
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gold_rail_cpu_sleep_0: cpu-sleep-1 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <702>;
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exit-latency-us = <1061>;
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min-residency-us = <4488>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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cluster_sleep_gold: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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};
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cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x42000144>;
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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};
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};
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};
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cpu0_opp_table: opp-table-cpu0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1267200000 {
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opp-hz = /bits/ 64 <1267200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1363200000 {
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opp-hz = /bits/ 64 <1363200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1459200000 {
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opp-hz = /bits/ 64 <1459200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1536000000 {
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opp-hz = /bits/ 64 <1536000000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1632000000 {
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opp-hz = /bits/ 64 <1632000000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1708800000 {
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opp-hz = /bits/ 64 <1708800000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1785600000 {
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opp-hz = /bits/ 64 <1785600000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1862400000 {
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opp-hz = /bits/ 64 <1862400000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1939200000 {
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opp-hz = /bits/ 64 <1939200000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-2016000000 {
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opp-hz = /bits/ 64 <2016000000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-2112000000 {
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opp-hz = /bits/ 64 <2112000000>;
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opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
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};
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opp-2188800000 {
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opp-hz = /bits/ 64 <2188800000>;
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opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
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};
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opp-2265600000 {
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opp-hz = /bits/ 64 <2265600000>;
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opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
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};
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opp-2361600000 {
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opp-hz = /bits/ 64 <2361600000>;
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opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
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};
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opp-2457600000 {
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opp-hz = /bits/ 64 <2457600000>;
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opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
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};
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opp-2553600000 {
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opp-hz = /bits/ 64 <2553600000>;
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opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
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};
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};
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cpu4_opp_table: opp-table-cpu4 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1267200000 {
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opp-hz = /bits/ 64 <1267200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1363200000 {
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opp-hz = /bits/ 64 <1363200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1459200000 {
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opp-hz = /bits/ 64 <1459200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1536000000 {
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opp-hz = /bits/ 64 <1536000000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
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};
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opp-1632000000 {
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opp-hz = /bits/ 64 <1632000000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1708800000 {
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opp-hz = /bits/ 64 <1708800000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1785600000 {
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opp-hz = /bits/ 64 <1785600000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1862400000 {
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opp-hz = /bits/ 64 <1862400000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
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};
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opp-1939200000 {
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opp-hz = /bits/ 64 <1939200000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
|
|
};
|
|
|
|
opp-2016000000 {
|
|
opp-hz = /bits/ 64 <2016000000>;
|
|
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
|
|
};
|
|
|
|
opp-2112000000 {
|
|
opp-hz = /bits/ 64 <2112000000>;
|
|
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
|
|
};
|
|
|
|
opp-2188800000 {
|
|
opp-hz = /bits/ 64 <2188800000>;
|
|
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
|
|
};
|
|
|
|
opp-2265600000 {
|
|
opp-hz = /bits/ 64 <2265600000>;
|
|
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
|
|
};
|
|
|
|
opp-2361600000 {
|
|
opp-hz = /bits/ 64 <2361600000>;
|
|
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
|
|
};
|
|
|
|
opp-2457600000 {
|
|
opp-hz = /bits/ 64 <2457600000>;
|
|
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
|
|
};
|
|
|
|
opp-2553600000 {
|
|
opp-hz = /bits/ 64 <2553600000>;
|
|
opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
|
|
};
|
|
};
|
|
|
|
dummy-sink {
|
|
compatible = "arm,coresight-dummy-sink";
|
|
|
|
in-ports {
|
|
port {
|
|
eud_in: endpoint {
|
|
remote-endpoint =
|
|
<&swao_rep_out1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
firmware {
|
|
scm {
|
|
compatible = "qcom,scm-sa8775p", "qcom,scm";
|
|
qcom,dload-mode = <&tcsr 0x13000>;
|
|
memory-region = <&tz_ffi_mem>;
|
|
};
|
|
};
|
|
|
|
aggre1_noc: interconnect-aggre1-noc {
|
|
compatible = "qcom,sa8775p-aggre1-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect-aggre2-noc {
|
|
compatible = "qcom,sa8775p-aggre2-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
clk_virt: interconnect-clk-virt {
|
|
compatible = "qcom,sa8775p-clk-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
config_noc: interconnect-config-noc {
|
|
compatible = "qcom,sa8775p-config-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect-dc-noc {
|
|
compatible = "qcom,sa8775p-dc-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect-gem-noc {
|
|
compatible = "qcom,sa8775p-gem-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gpdsp_anoc: interconnect-gpdsp-anoc {
|
|
compatible = "qcom,sa8775p-gpdsp-anoc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect-lpass-ag-noc {
|
|
compatible = "qcom,sa8775p-lpass-ag-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect-mc-virt {
|
|
compatible = "qcom,sa8775p-mc-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect-mmss-noc {
|
|
compatible = "qcom,sa8775p-mmss-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
nspa_noc: interconnect-nspa-noc {
|
|
compatible = "qcom,sa8775p-nspa-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
nspb_noc: interconnect-nspb-noc {
|
|
compatible = "qcom,sa8775p-nspb-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie_anoc: interconnect-pcie-anoc {
|
|
compatible = "qcom,sa8775p-pcie-anoc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect-system-noc {
|
|
compatible = "qcom,sa8775p-system-noc";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
/* Will be updated by the bootloader. */
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x80000000 0x0 0x0>;
|
|
};
|
|
|
|
qup_opp_table_100mhz: opp-table-qup100mhz {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
cpu_pd0: power-domain-cpu0 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_0_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd1: power-domain-cpu1 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_0_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd2: power-domain-cpu2 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_0_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd3: power-domain-cpu3 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_0_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd4: power-domain-cpu4 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_1_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd5: power-domain-cpu5 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_1_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd6: power-domain-cpu6 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_1_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd7: power-domain-cpu7 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_1_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>,
|
|
<&gold_rail_cpu_sleep_0>;
|
|
};
|
|
|
|
cluster_0_pd: power-domain-cluster0 {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&cluster_sleep_gold>;
|
|
power-domains = <&system_pd>;
|
|
};
|
|
|
|
cluster_1_pd: power-domain-cluster1 {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&cluster_sleep_gold>;
|
|
power-domains = <&system_pd>;
|
|
};
|
|
|
|
system_pd: power-domain-system {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&cluster_sleep_apss_rsc_pc>;
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
sail_ss_mem: sail-ss@80000000 {
|
|
reg = <0x0 0x80000000 0x0 0x10000000>;
|
|
no-map;
|
|
};
|
|
|
|
hyp_mem: hyp@90000000 {
|
|
reg = <0x0 0x90000000 0x0 0x600000>;
|
|
no-map;
|
|
};
|
|
|
|
xbl_boot_mem: xbl-boot@90600000 {
|
|
reg = <0x0 0x90600000 0x0 0x200000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_image_mem: aop-image@90800000 {
|
|
reg = <0x0 0x90800000 0x0 0x60000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_cmd_db_mem: aop-cmd-db@90860000 {
|
|
compatible = "qcom,cmd-db";
|
|
reg = <0x0 0x90860000 0x0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
uefi_log: uefi-log@908b0000 {
|
|
reg = <0x0 0x908b0000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
ddr_training_checksum: ddr-training-checksum@908c0000 {
|
|
reg = <0x0 0x908c0000 0x0 0x1000>;
|
|
no-map;
|
|
};
|
|
|
|
reserved_mem: reserved@908f0000 {
|
|
reg = <0x0 0x908f0000 0x0 0xe000>;
|
|
no-map;
|
|
};
|
|
|
|
secdata_apss_mem: secdata-apss@908fe000 {
|
|
reg = <0x0 0x908fe000 0x0 0x2000>;
|
|
no-map;
|
|
};
|
|
|
|
smem_mem: smem@90900000 {
|
|
compatible = "qcom,smem";
|
|
reg = <0x0 0x90900000 0x0 0x200000>;
|
|
no-map;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
|
|
reg = <0x0 0x90c00000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
sail_mailbox_mem: sail-ss@90d00000 {
|
|
reg = <0x0 0x90d00000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
sail_ota_mem: sail-ss@90e00000 {
|
|
reg = <0x0 0x90e00000 0x0 0x300000>;
|
|
no-map;
|
|
};
|
|
|
|
aoss_backup_mem: aoss-backup@91b00000 {
|
|
reg = <0x0 0x91b00000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
cpucp_backup_mem: cpucp-backup@91b40000 {
|
|
reg = <0x0 0x91b40000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
tz_config_backup_mem: tz-config-backup@91b80000 {
|
|
reg = <0x0 0x91b80000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
ddr_training_data_mem: ddr-training-data@91b90000 {
|
|
reg = <0x0 0x91b90000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
cdt_data_backup_mem: cdt-data-backup@91ba0000 {
|
|
reg = <0x0 0x91ba0000 0x0 0x1000>;
|
|
no-map;
|
|
};
|
|
|
|
tz_ffi_mem: tz-ffi@91c00000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0x91c00000 0x0 0x1400000>;
|
|
no-map;
|
|
};
|
|
|
|
lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
|
|
reg = <0x0 0x93b00000 0x0 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
|
|
reg = <0x0 0x94a00000 0x0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_camera_mem: pil-camera@95200000 {
|
|
reg = <0x0 0x95200000 0x0 0x500000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_adsp_mem: pil-adsp@95c00000 {
|
|
reg = <0x0 0x95c00000 0x0 0x1e00000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_gdsp0_mem: pil-gdsp0@97b00000 {
|
|
reg = <0x0 0x97b00000 0x0 0x1e00000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_gdsp1_mem: pil-gdsp1@99900000 {
|
|
reg = <0x0 0x99900000 0x0 0x1e00000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_cdsp0_mem: pil-cdsp0@9b800000 {
|
|
reg = <0x0 0x9b800000 0x0 0x1e00000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_gpu_mem: pil-gpu@9d600000 {
|
|
reg = <0x0 0x9d600000 0x0 0x2000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_cdsp1_mem: pil-cdsp1@9d700000 {
|
|
reg = <0x0 0x9d700000 0x0 0x1e00000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_cvp_mem: pil-cvp@9f500000 {
|
|
reg = <0x0 0x9f500000 0x0 0x700000>;
|
|
no-map;
|
|
};
|
|
|
|
pil_video_mem: pil-video@9fc00000 {
|
|
reg = <0x0 0x9fc00000 0x0 0x700000>;
|
|
no-map;
|
|
};
|
|
|
|
audio_mdf_mem: audio-mdf-region@ae000000 {
|
|
reg = <0x0 0xae000000 0x0 0x1000000>;
|
|
no-map;
|
|
};
|
|
|
|
firmware_mem: firmware-region@b0000000 {
|
|
reg = <0x0 0xb0000000 0x0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
hyptz_reserved_mem: hyptz-reserved@beb00000 {
|
|
reg = <0x0 0xbeb00000 0x0 0x11500000>;
|
|
no-map;
|
|
};
|
|
|
|
scmi_mem: scmi-region@d0000000 {
|
|
reg = <0x0 0xd0000000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
firmware_logs_mem: firmware-logs@d0040000 {
|
|
reg = <0x0 0xd0040000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
firmware_audio_mem: firmware-audio@d0050000 {
|
|
reg = <0x0 0xd0050000 0x0 0x4000>;
|
|
no-map;
|
|
};
|
|
|
|
firmware_reserved_mem: firmware-reserved@d0054000 {
|
|
reg = <0x0 0xd0054000 0x0 0x9c000>;
|
|
no-map;
|
|
};
|
|
|
|
firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
|
|
reg = <0x0 0xd00f0000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
tags_mem: tags@d0100000 {
|
|
reg = <0x0 0xd0100000 0x0 0x1200000>;
|
|
no-map;
|
|
};
|
|
|
|
qtee_mem: qtee@d1300000 {
|
|
reg = <0x0 0xd1300000 0x0 0x500000>;
|
|
no-map;
|
|
};
|
|
|
|
deepsleep_backup_mem: deepsleep-backup@d1800000 {
|
|
reg = <0x0 0xd1800000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
trusted_apps_mem: trusted-apps@d1900000 {
|
|
reg = <0x0 0xd1900000 0x0 0x3800000>;
|
|
no-map;
|
|
};
|
|
|
|
tz_stat_mem: tz-stat@db100000 {
|
|
reg = <0x0 0xdb100000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
cpucp_fw_mem: cpucp-fw@db200000 {
|
|
reg = <0x0 0xdb200000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
smp2p_adsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_adsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp0 {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
smp2p_cdsp0_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_cdsp0_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp1 {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <12>;
|
|
|
|
smp2p_cdsp1_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_cdsp1_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-gpdsp0 {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <17>;
|
|
|
|
smp2p_gpdsp0_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_gpdsp0_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-gpdsp1 {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <18>;
|
|
|
|
smp2p_gpdsp1_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_gpdsp1_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc@0 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0 0 0 0x10 0>;
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,sa8775p-gcc";
|
|
reg = <0x0 0x00100000 0x0 0xc7018>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<&usb_0_qmpphy>,
|
|
<&usb_1_qmpphy>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<&pcie0_phy>,
|
|
<&pcie1_phy>,
|
|
<0>,
|
|
<0>,
|
|
<0>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
};
|
|
|
|
ipcc: mailbox@408000 {
|
|
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
|
|
reg = <0x0 0x00408000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
gpi_dma2: dma-controller@800000 {
|
|
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00800000 0x0 0x60000>;
|
|
#dma-cells = <3>;
|
|
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xfff>;
|
|
iommus = <&apps_smmu 0x5b6 0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_2: geniqup@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x008c0000 0x0 0x6000>;
|
|
ranges;
|
|
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
iommus = <&apps_smmu 0x5a3 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
|
|
i2c14: i2c@880000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x880000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c14_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi14: spi@880000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x880000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi14_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart14: serial@880000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00880000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart14_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c@884000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x884000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c15_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi15: spi@884000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x884000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi15_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart15: serial@884000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00884000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart15_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c16: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x888000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c16_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi16: spi@888000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00888000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi16_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart16: serial@888000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00888000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart16_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c17: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x88c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c17_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi17: spi@88c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x88c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi17_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart17: serial@88c000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x0088c000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart17_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c18: i2c@890000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00890000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c18_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi18: spi@890000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x890000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi18_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart18: serial@890000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00890000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart18_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c19: i2c@894000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x894000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c19_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi19: spi@894000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x894000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi19_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart19: serial@894000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00894000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart19_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c20: i2c@898000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x898000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c20_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi20: spi@898000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x898000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi20_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart20: serial@898000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00898000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart20_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
gpi_dma0: dma-controller@900000 {
|
|
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00900000 0x0 0x60000>;
|
|
#dma-cells = <3>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xfff>;
|
|
iommus = <&apps_smmu 0x416 0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_0: geniqup@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x9c0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x403 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@980000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x980000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c0_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@980000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x980000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi0_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@980000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x980000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart0_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@984000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x984000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c1_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@984000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x984000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi1_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@984000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x984000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart1_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@988000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x988000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c2_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@988000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x988000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi2_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@988000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x988000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart2_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@98c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x98c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c3_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@98c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x98c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi3_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@98c000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x98c000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart3_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@990000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x990000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c4_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@990000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x990000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi4_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@990000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x990000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart4_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@994000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c5_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@994000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi5_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@994000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart5_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma1: dma-controller@a00000 {
|
|
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00a00000 0x0 0x60000>;
|
|
#dma-cells = <3>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x456 0x0>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xfff>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x443 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c7: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c7_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi7_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@a80000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a80000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
pinctrl-0 = <&qup_uart7_default>;
|
|
pinctrl-names = "default";
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa84000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c8_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa84000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi8_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart8: serial@a84000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a84000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
pinctrl-0 = <&qup_uart8_default>;
|
|
pinctrl-names = "default";
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c9_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi9_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart9: serial@a88000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart9_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa8c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c10_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@a8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa8c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi10_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart10: serial@a8c000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a8c000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
pinctrl-0 = <&qup_uart10_default>;
|
|
pinctrl-names = "default";
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 0
|
|
&clk_virt SLAVE_QUP_CORE_1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0
|
|
&config_noc SLAVE_QUP_1 0>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa90000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c11_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi11: spi@a90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa90000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi11_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart11: serial@a90000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
pinctrl-0 = <&qup_uart11_default>;
|
|
pinctrl-names = "default";
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@a94000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa94000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c12_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi12: spi@a94000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa94000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi12_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart12: serial@a94000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a94000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_uart12_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c@a98000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa98000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c13_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
|
|
};
|
|
};
|
|
|
|
gpi_dma3: dma-controller@b00000 {
|
|
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00b00000 0x0 0x58000>;
|
|
#dma-cells = <3>;
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x056 0x0>;
|
|
dma-channels = <4>;
|
|
dma-channel-mask = <0xf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_3: geniqup@bc0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0xbc0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x43 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c21: i2c@b80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xb80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_i2c21_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma3 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi21: spi@b80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xb80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
|
clock-names = "se";
|
|
pinctrl-0 = <&qup_spi21_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma3 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart21: serial@b80000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00b80000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
pinctrl-0 = <&qup_uart21_default>;
|
|
pinctrl-names = "default";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
rng: rng@10d2000 {
|
|
compatible = "qcom,sa8775p-trng", "qcom,trng";
|
|
reg = <0 0x010d2000 0 0x1000>;
|
|
};
|
|
|
|
ufs_mem_hc: ufshc@1d84000 {
|
|
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
|
reg = <0x0 0x01d84000 0x0 0x3000>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufs_mem_phy>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <2>;
|
|
#reset-cells = <1>;
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
iommus = <&apps_smmu 0x100 0x0>;
|
|
dma-coherent;
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
clock-names = "core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
freq-table-hz = <75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
qcom,ice = <&ice>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_phy: phy@1d87000 {
|
|
compatible = "qcom,sa8775p-qmp-ufs-phy";
|
|
reg = <0x0 0x01d87000 0x0 0xe10>;
|
|
/*
|
|
* Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
|
|
* enables the CXO clock to eDP *and* UFS PHY.
|
|
*/
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&gcc GCC_EDP_REF_CLKREF_EN>;
|
|
clock-names = "ref", "ref_aux", "qref";
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
resets = <&ufs_mem_hc 0>;
|
|
reset-names = "ufsphy";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ice: crypto@1d88000 {
|
|
compatible = "qcom,sa8775p-inline-crypto-engine",
|
|
"qcom,inline-crypto-engine";
|
|
reg = <0x0 0x01d88000 0x0 0x18000>;
|
|
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
|
};
|
|
|
|
cryptobam: dma-controller@1dc4000 {
|
|
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
|
reg = <0x0 0x01dc4000 0x0 0x28000>;
|
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
qcom,num-ees = <4>;
|
|
num-channels = <20>;
|
|
qcom,controlled-remotely;
|
|
iommus = <&apps_smmu 0x480 0x00>,
|
|
<&apps_smmu 0x481 0x00>;
|
|
};
|
|
|
|
ctcu@4001000 {
|
|
compatible = "qcom,sa8775p-ctcu";
|
|
reg = <0x0 0x04001000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
ctcu_in0: endpoint {
|
|
remote-endpoint = <&etr0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
ctcu_in1: endpoint {
|
|
remote-endpoint = <&etr1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
stm: stm@4002000 {
|
|
compatible = "arm,coresight-stm", "arm,primecell";
|
|
reg = <0x0 0x4002000 0x0 0x1000>,
|
|
<0x0 0x16280000 0x0 0x180000>;
|
|
reg-names = "stm-base", "stm-stimulus-base";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
stm_out: endpoint {
|
|
remote-endpoint =
|
|
<&funnel0_in7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4003000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4003000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <32>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
status = "disabled";
|
|
|
|
out-ports {
|
|
port {
|
|
qdss_tpdm0_out: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_tpda_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@4004000 {
|
|
compatible = "qcom,coresight-tpda", "arm,primecell";
|
|
reg = <0x0 0x4004000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
qdss_tpda_out: endpoint {
|
|
remote-endpoint =
|
|
<&funnel0_in6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
qdss_tpda_in0: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_tpdm0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
qdss_tpda_in1: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_tpdm1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@400f000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x400f000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <32>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
qdss_tpdm1_out: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_tpda_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@4041000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x4041000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
funnel0_out: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_funnel_in0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel0_in6: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_tpda_out>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
funnel0_in7: endpoint {
|
|
remote-endpoint =
|
|
<&stm_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@4042000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x4042000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
funnel1_out: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_funnel_in1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
funnel1_in4: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@4045000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x4045000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
qdss_funnel_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_funnel_in7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
qdss_funnel_in0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
qdss_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@4046000 {
|
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
|
reg = <0x0 0x04046000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
qdss_rep_in: endpoint {
|
|
remote-endpoint = <&swao_rep_out0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
qdss_rep_out0: endpoint {
|
|
remote-endpoint = <&etr_rep_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etr: tmc@4048000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x0 0x04048000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&apps_smmu 0x04c0 0x00>;
|
|
|
|
arm,scatter-gather;
|
|
|
|
in-ports {
|
|
port {
|
|
etr0_in: endpoint {
|
|
remote-endpoint = <&etr_rep_out0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
etr0_out: endpoint {
|
|
remote-endpoint = <&ctcu_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@404e000 {
|
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
|
reg = <0x0 0x0404e000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
etr_rep_in: endpoint {
|
|
remote-endpoint = <&qdss_rep_out0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
etr_rep_out0: endpoint {
|
|
remote-endpoint = <&etr0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
etr_rep_out1: endpoint {
|
|
remote-endpoint = <&etr1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etr1: tmc@404f000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x0 0x0404f000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&apps_smmu 0x04a0 0x40>;
|
|
|
|
arm,scatter-gather;
|
|
arm,buffer-size = <0x400000>;
|
|
|
|
in-ports {
|
|
port {
|
|
etr1_in: endpoint {
|
|
remote-endpoint = <&etr_rep_out1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
etr1_out: endpoint {
|
|
remote-endpoint = <&ctcu_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@4b04000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x4b04000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_funnel_out: endpoint {
|
|
remote-endpoint =
|
|
<&etf0_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
aoss_funnel_in6: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_out>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
aoss_funnel_in7: endpoint {
|
|
remote-endpoint =
|
|
<&qdss_funnel_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etf: tmc@4b05000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x0 0x4b05000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
etf0_out: endpoint {
|
|
remote-endpoint =
|
|
<&swao_rep_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
port {
|
|
etf0_in: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_funnel_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@4b06000 {
|
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
|
reg = <0x0 0x4b06000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
swao_rep_out0: endpoint {
|
|
remote-endpoint = <&qdss_rep_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
swao_rep_out1: endpoint {
|
|
remote-endpoint =
|
|
<&eud_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
port {
|
|
swao_rep_in: endpoint {
|
|
remote-endpoint =
|
|
<&etf0_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@4b08000 {
|
|
compatible = "qcom,coresight-tpda", "arm,primecell";
|
|
reg = <0x0 0x4b08000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpda_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_funnel_in6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
aoss_tpda_in0: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpdm0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
aoss_tpda_in1: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpdm1_out>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
aoss_tpda_in2: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpdm2_out>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
aoss_tpda_in3: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpdm3_out>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
aoss_tpda_in4: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpdm4_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4b09000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4b09000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <64>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpdm0_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4b0a000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4b0a000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <64>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpdm1_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4b0b000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4b0b000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <64>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpdm2_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_in2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4b0c000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4b0c000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <64>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpdm3_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_in3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@4b0d000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x4b0d000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,dsb-element-bits = <32>;
|
|
qcom,dsb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
aoss_tpdm4_out: endpoint {
|
|
remote-endpoint =
|
|
<&aoss_tpda_in4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss_cti: cti@4b13000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x0 0x4b13000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
etm@6040000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6040000 0x0 0x1000>;
|
|
cpu = <&cpu0>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm0_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6140000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6140000 0x0 0x1000>;
|
|
cpu = <&cpu1>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm1_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6240000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6240000 0x0 0x1000>;
|
|
cpu = <&cpu2>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm2_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6340000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6340000 0x0 0x1000>;
|
|
cpu = <&cpu3>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm3_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6440000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6440000 0x0 0x1000>;
|
|
cpu = <&cpu4>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm4_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6540000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6540000 0x0 0x1000>;
|
|
cpu = <&cpu5>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm5_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6640000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6640000 0x0 0x1000>;
|
|
cpu = <&cpu6>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm6_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@6740000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x0 0x6740000 0x0 0x1000>;
|
|
cpu = <&cpu7>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
arm,coresight-loses-context-with-cpu;
|
|
qcom,skip-power-up;
|
|
|
|
out-ports {
|
|
port {
|
|
etm7_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_in7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6800000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x6800000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
apss_funnel0_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel1_in0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
apss_funnel0_in0: endpoint {
|
|
remote-endpoint =
|
|
<&etm0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
apss_funnel0_in1: endpoint {
|
|
remote-endpoint =
|
|
<&etm1_out>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
apss_funnel0_in2: endpoint {
|
|
remote-endpoint =
|
|
<&etm2_out>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
apss_funnel0_in3: endpoint {
|
|
remote-endpoint =
|
|
<&etm3_out>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
apss_funnel0_in4: endpoint {
|
|
remote-endpoint =
|
|
<&etm4_out>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
apss_funnel0_in5: endpoint {
|
|
remote-endpoint =
|
|
<&etm5_out>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
apss_funnel0_in6: endpoint {
|
|
remote-endpoint =
|
|
<&etm6_out>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
apss_funnel0_in7: endpoint {
|
|
remote-endpoint =
|
|
<&etm7_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6810000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x0 0x6810000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
apss_funnel1_out: endpoint {
|
|
remote-endpoint =
|
|
<&funnel1_in4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
apss_funnel1_in0: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel0_out>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
apss_funnel1_in3: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6860000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x6860000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <64>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpdm3_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_in3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6861000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x6861000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,dsb-element-bits = <32>;
|
|
qcom,dsb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpdm4_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_in4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@6863000 {
|
|
compatible = "qcom,coresight-tpda", "arm,primecell";
|
|
reg = <0x0 0x6863000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpda_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel1_in3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
apss_tpda_in0: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpdm0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
apss_tpda_in1: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpdm1_out>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
apss_tpda_in2: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpdm2_out>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
apss_tpda_in3: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpdm3_out>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
apss_tpda_in4: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpdm4_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@68a0000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x68a0000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <32>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpdm0_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@68b0000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x68b0000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,cmb-element-bits = <32>;
|
|
qcom,cmb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpdm1_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@68c0000 {
|
|
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
|
reg = <0x0 0x68c0000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,dsb-element-bits = <32>;
|
|
qcom,dsb-msrs-num = <32>;
|
|
|
|
out-ports {
|
|
port {
|
|
apss_tpdm2_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_tpda_in2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_0_hsphy: phy@88e4000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e4000 0 0x120>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_0_qmpphy: phy@88e8000 {
|
|
compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
|
|
reg = <0 0x088e8000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_CLKREF_EN>,
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "aux", "ref", "com_aux", "pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
|
|
reset-names = "phy", "phy_phy";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb3_prim_phy_pipe_clk_src";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_0: usb@a6f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a6f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"hs_phy_irq",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_0_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a600000 0 0xe000>;
|
|
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x080 0x0>;
|
|
phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|
|
};
|
|
|
|
usb_1_hsphy: phy@88e6000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e6000 0 0x120>;
|
|
clocks = <&gcc GCC_USB_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_1_qmpphy: phy@88ea000 {
|
|
compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
|
|
reg = <0 0x088ea000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_CLKREF_EN>,
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
|
clock-names = "aux", "ref", "com_aux", "pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
|
reset-names = "phy", "phy_phy";
|
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb3_sec_phy_pipe_clk_src";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_1: usb@a8f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a8f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"hs_phy_irq",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_1_dwc3: usb@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a800000 0 0xe000>;
|
|
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x0a0 0x0>;
|
|
phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|
|
};
|
|
|
|
usb_2_hsphy: phy@88e7000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e7000 0 0x120>;
|
|
clocks = <&gcc GCC_USB_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_2: usb@a4f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a4f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB20_SLEEP_CLK>,
|
|
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "pwr_event",
|
|
"hs_phy_irq",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB20_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB20_PRIM_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_2_dwc3: usb@a400000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a400000 0 0xe000>;
|
|
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x020 0x0>;
|
|
phys = <&usb_2_hsphy>;
|
|
phy-names = "usb2-phy";
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x01f40000 0x0 0x20000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "qcom,sa8775p-tcsr", "syscon";
|
|
reg = <0x0 0x1fc0000 0x0 0x30000>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sa8775p-gpucc";
|
|
reg = <0x0 0x03d90000 0x0 0xa000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_gpu_gpll0_clk_src",
|
|
"gcc_gpu_gpll0_div_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
adreno_smmu: iommu@3da0000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
|
|
"qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x03da0000 0x0 0x20000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
dma-coherent;
|
|
power-domains = <&gpucc GPU_CC_CX_GDSC>;
|
|
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_HUB_AON_CLK>;
|
|
clock-names = "gcc_gpu_memnoc_gfx_clk",
|
|
"gcc_gpu_snoc_dvm_gfx_clk",
|
|
"gpu_cc_ahb_clk",
|
|
"gpu_cc_hlos1_vote_gpu_smmu_clk",
|
|
"gpu_cc_cx_gmu_clk",
|
|
"gpu_cc_hub_cx_int_clk",
|
|
"gpu_cc_hub_aon_clk";
|
|
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
serdes0: phy@8901000 {
|
|
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
|
|
reg = <0x0 0x08901000 0x0 0xe10>;
|
|
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
|
|
clock-names = "sgmi_ref";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serdes1: phy@8902000 {
|
|
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
|
|
reg = <0x0 0x08902000 0x0 0xe10>;
|
|
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
|
|
clock-names = "sgmi_ref";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu@9091000 {
|
|
compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
|
|
reg = <0x0 0x9091000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
|
|
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
|
|
operating-points-v2 = <&llcc_bwmon_opp_table>;
|
|
|
|
llcc_bwmon_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-0 {
|
|
opp-peak-kBps = <762000>;
|
|
};
|
|
|
|
opp-1 {
|
|
opp-peak-kBps = <1720000>;
|
|
};
|
|
|
|
opp-2 {
|
|
opp-peak-kBps = <2086000>;
|
|
};
|
|
|
|
opp-3 {
|
|
opp-peak-kBps = <2601000>;
|
|
};
|
|
|
|
opp-4 {
|
|
opp-peak-kBps = <2929000>;
|
|
};
|
|
|
|
opp-5 {
|
|
opp-peak-kBps = <5931000>;
|
|
};
|
|
|
|
opp-6 {
|
|
opp-peak-kBps = <6515000>;
|
|
};
|
|
|
|
opp-7 {
|
|
opp-peak-kBps = <7984000>;
|
|
};
|
|
|
|
opp-8 {
|
|
opp-peak-kBps = <10437000>;
|
|
};
|
|
|
|
opp-9 {
|
|
opp-peak-kBps = <12195000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmu@90b5400 {
|
|
compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
|
|
reg = <0x0 0x90b5400 0x0 0x600>;
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
|
|
operating-points-v2 = <&cpu_bwmon_opp_table>;
|
|
|
|
cpu_bwmon_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-0 {
|
|
opp-peak-kBps = <9155000>;
|
|
};
|
|
|
|
opp-1 {
|
|
opp-peak-kBps = <12298000>;
|
|
};
|
|
|
|
opp-2 {
|
|
opp-peak-kBps = <14236000>;
|
|
};
|
|
|
|
opp-3 {
|
|
opp-peak-kBps = <16265000>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
pmu@90b6400 {
|
|
compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
|
|
reg = <0x0 0x90b6400 0x0 0x600>;
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
|
|
operating-points-v2 = <&cpu_bwmon_opp_table>;
|
|
};
|
|
|
|
llcc: system-cache-controller@9200000 {
|
|
compatible = "qcom,sa8775p-llcc";
|
|
reg = <0x0 0x09200000 0x0 0x80000>,
|
|
<0x0 0x09300000 0x0 0x80000>,
|
|
<0x0 0x09400000 0x0 0x80000>,
|
|
<0x0 0x09500000 0x0 0x80000>,
|
|
<0x0 0x09600000 0x0 0x80000>,
|
|
<0x0 0x09700000 0x0 0x80000>,
|
|
<0x0 0x09a00000 0x0 0x80000>;
|
|
reg-names = "llcc0_base",
|
|
"llcc1_base",
|
|
"llcc2_base",
|
|
"llcc3_base",
|
|
"llcc4_base",
|
|
"llcc5_base",
|
|
"llcc_broadcast_base";
|
|
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iris: video-codec@aa00000 {
|
|
compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris";
|
|
|
|
reg = <0x0 0x0aa00000 0x0 0xf0000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
|
|
<&videocc VIDEO_CC_MVS0_GDSC>,
|
|
<&rpmhpd SA8775P_MX>,
|
|
<&rpmhpd SA8775P_MMCX>;
|
|
power-domain-names = "venus",
|
|
"vcodec0",
|
|
"mxc",
|
|
"mmcx";
|
|
operating-points-v2 = <&iris_opp_table>;
|
|
|
|
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
|
|
<&videocc VIDEO_CC_MVS0C_CLK>,
|
|
<&videocc VIDEO_CC_MVS0_CLK>;
|
|
clock-names = "iface",
|
|
"core",
|
|
"vcodec0_core";
|
|
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "cpu-cfg",
|
|
"video-mem";
|
|
|
|
memory-region = <&pil_video_mem>;
|
|
|
|
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
|
|
reset-names = "bus";
|
|
|
|
iommus = <&apps_smmu 0x0880 0x0400>,
|
|
<&apps_smmu 0x0887 0x0400>;
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
|
|
iris_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-366000000 {
|
|
opp-hz = /bits/ 64 <366000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>,
|
|
<&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-444000000 {
|
|
opp-hz = /bits/ 64 <444000000>;
|
|
required-opps = <&rpmhpd_opp_nom>,
|
|
<&rpmhpd_opp_nom>;
|
|
};
|
|
|
|
opp-533000000 {
|
|
opp-hz = /bits/ 64 <533000000>;
|
|
required-opps = <&rpmhpd_opp_turbo>,
|
|
<&rpmhpd_opp_turbo>;
|
|
};
|
|
|
|
opp-560000000 {
|
|
opp-hz = /bits/ 64 <560000000>;
|
|
required-opps = <&rpmhpd_opp_turbo_l1>,
|
|
<&rpmhpd_opp_turbo_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
videocc: clock-controller@abf0000 {
|
|
compatible = "qcom,sa8775p-videocc";
|
|
reg = <0x0 0x0abf0000 0x0 0x10000>;
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,sa8775p-camcc";
|
|
reg = <0x0 0x0ade0000 0x0 0x20000>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
mdss0: display-subsystem@ae00000 {
|
|
compatible = "qcom,sa8775p-mdss";
|
|
reg = <0x0 0x0ae00000 0x0 0x1000>;
|
|
reg-names = "mdss";
|
|
|
|
/* same path used twice */
|
|
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "mdp0-mem",
|
|
"mdp1-mem",
|
|
"cpu-cfg";
|
|
|
|
resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
|
|
|
|
power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
|
|
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
iommus = <&apps_smmu 0x1000 0x402>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
mdss0_mdp: display-controller@ae01000 {
|
|
compatible = "qcom,sa8775p-dpu";
|
|
reg = <0x0 0x0ae01000 0x0 0x8f000>,
|
|
<0x0 0x0aeb0000 0x0 0x3000>;
|
|
reg-names = "mdp", "vbif";
|
|
|
|
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
|
|
clock-names = "bus",
|
|
"iface",
|
|
"lut",
|
|
"core",
|
|
"vsync";
|
|
|
|
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
operating-points-v2 = <&mdss0_mdp_opp_table>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
|
|
interrupt-parent = <&mdss0>;
|
|
interrupts = <0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
dpu_intf0_out: endpoint {
|
|
remote-endpoint = <&mdss0_dp0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
dpu_intf4_out: endpoint {
|
|
remote-endpoint = <&mdss0_dp1_in>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
dpu_intf1_out: endpoint {
|
|
remote-endpoint = <&mdss0_dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
|
|
dpu_intf2_out: endpoint {
|
|
remote-endpoint = <&mdss0_dsi1_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss0_mdp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-375000000 {
|
|
opp-hz = /bits/ 64 <375000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
|
|
opp-575000000 {
|
|
opp-hz = /bits/ 64 <575000000>;
|
|
required-opps = <&rpmhpd_opp_turbo>;
|
|
};
|
|
|
|
opp-650000000 {
|
|
opp-hz = /bits/ 64 <650000000>;
|
|
required-opps = <&rpmhpd_opp_turbo_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss0_dsi0: dsi@ae94000 {
|
|
compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0x0 0x0ae94000 0x0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupt-parent = <&mdss0>;
|
|
interrupts = <4>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
|
|
phys = <&mdss0_dsi0_phy>;
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss0_dsi0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf1_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss0_dsi0_out: endpoint{ };
|
|
};
|
|
};
|
|
|
|
mdss_dsi_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-358000000 {
|
|
opp-hz = /bits/ 64 <358000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss0_dsi0_phy: phy@ae94400 {
|
|
compatible = "qcom,sa8775p-dsi-phy-5nm";
|
|
reg = <0x0 0x0ae94400 0x0 0x200>,
|
|
<0x0 0x0ae94600 0x0 0x280>,
|
|
<0x0 0x0ae94900 0x0 0x27c>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface", "ref";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss0_dsi1: dsi@ae96000 {
|
|
compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0x0 0x0ae96000 0x0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupt-parent = <&mdss0>;
|
|
interrupts = <5>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
|
|
phys = <&mdss0_dsi1_phy>;
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss0_dsi1_in: endpoint {
|
|
remote-endpoint = <&dpu_intf2_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss0_dsi1_out: endpoint { };
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss0_dsi1_phy: phy@ae96400 {
|
|
compatible = "qcom,sa8775p-dsi-phy-5nm";
|
|
reg = <0x0 0x0ae96400 0x0 0x200>,
|
|
<0x0 0x0ae96600 0x0 0x280>,
|
|
<0x0 0x0ae96900 0x0 0x27c>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface", "ref";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss0_dp0_phy: phy@aec2a00 {
|
|
compatible = "qcom,sa8775p-edp-phy";
|
|
|
|
reg = <0x0 0x0aec2a00 0x0 0x200>,
|
|
<0x0 0x0aec2200 0x0 0xd0>,
|
|
<0x0 0x0aec2600 0x0 0xd0>,
|
|
<0x0 0x0aec2000 0x0 0x1c8>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
|
|
clock-names = "aux",
|
|
"cfg_ahb";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss0_dp1_phy: phy@aec5a00 {
|
|
compatible = "qcom,sa8775p-edp-phy";
|
|
|
|
reg = <0x0 0x0aec5a00 0x0 0x200>,
|
|
<0x0 0x0aec5200 0x0 0xd0>,
|
|
<0x0 0x0aec5600 0x0 0xd0>,
|
|
<0x0 0x0aec5000 0x0 0x1c8>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
|
|
clock-names = "aux",
|
|
"cfg_ahb";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss0_dp0: displayport-controller@af54000 {
|
|
compatible = "qcom,sa8775p-dp";
|
|
|
|
reg = <0x0 0x0af54000 0x0 0x104>,
|
|
<0x0 0x0af54200 0x0 0x0c0>,
|
|
<0x0 0x0af55000 0x0 0x770>,
|
|
<0x0 0x0af56000 0x0 0x09c>,
|
|
<0x0 0x0af57000 0x0 0x09c>;
|
|
|
|
interrupt-parent = <&mdss0>;
|
|
interrupts = <12>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
|
clock-names = "core_iface",
|
|
"core_aux",
|
|
"ctrl_link",
|
|
"ctrl_link_iface",
|
|
"stream_pixel";
|
|
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
|
|
phys = <&mdss0_dp0_phy>;
|
|
phy-names = "dp";
|
|
|
|
operating-points-v2 = <&dp_opp_table>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss0_dp0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss0_dp0_out: endpoint { };
|
|
};
|
|
};
|
|
|
|
dp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-270000000 {
|
|
opp-hz = /bits/ 64 <270000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-540000000 {
|
|
opp-hz = /bits/ 64 <540000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-810000000 {
|
|
opp-hz = /bits/ 64 <810000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss0_dp1: displayport-controller@af5c000 {
|
|
compatible = "qcom,sa8775p-dp";
|
|
|
|
reg = <0x0 0x0af5c000 0x0 0x104>,
|
|
<0x0 0x0af5c200 0x0 0x0c0>,
|
|
<0x0 0x0af5d000 0x0 0x770>,
|
|
<0x0 0x0af5e000 0x0 0x09c>,
|
|
<0x0 0x0af5f000 0x0 0x09c>;
|
|
|
|
interrupt-parent = <&mdss0>;
|
|
interrupts = <13>;
|
|
|
|
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
|
|
clock-names = "core_iface",
|
|
"core_aux",
|
|
"ctrl_link",
|
|
"ctrl_link_iface",
|
|
"stream_pixel";
|
|
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
|
|
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
|
|
phys = <&mdss0_dp1_phy>;
|
|
phy-names = "dp";
|
|
|
|
operating-points-v2 = <&dp1_opp_table>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss0_dp1_in: endpoint {
|
|
remote-endpoint = <&dpu_intf4_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss0_dp1_out: endpoint { };
|
|
};
|
|
};
|
|
|
|
dp1_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-270000000 {
|
|
opp-hz = /bits/ 64 <270000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-540000000 {
|
|
opp-hz = /bits/ 64 <540000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-810000000 {
|
|
opp-hz = /bits/ 64 <810000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dispcc0: clock-controller@af00000 {
|
|
compatible = "qcom,sa8775p-dispcc0";
|
|
reg = <0x0 0x0af00000 0x0 0x20000>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
|
|
<&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
|
|
<&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
|
<&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
|
|
reg = <0x0 0x0b220000 0x0 0x30000>,
|
|
<0x0 0x17c000f0 0x0 0x64>;
|
|
qcom,pdc-ranges = <0 480 40>,
|
|
<40 140 14>,
|
|
<54 263 1>,
|
|
<55 306 4>,
|
|
<59 312 3>,
|
|
<62 374 2>,
|
|
<64 434 2>,
|
|
<66 438 2>,
|
|
<70 520 1>,
|
|
<73 523 1>,
|
|
<118 568 6>,
|
|
<124 609 3>,
|
|
<159 638 1>,
|
|
<160 720 3>,
|
|
<169 728 30>,
|
|
<199 416 2>,
|
|
<201 449 1>,
|
|
<202 89 1>,
|
|
<203 451 1>,
|
|
<204 462 1>,
|
|
<205 264 1>,
|
|
<206 579 1>,
|
|
<207 653 1>,
|
|
<208 656 1>,
|
|
<209 659 1>,
|
|
<210 122 1>,
|
|
<211 699 1>,
|
|
<212 705 1>,
|
|
<213 450 1>,
|
|
<214 643 2>,
|
|
<216 646 5>,
|
|
<221 390 5>,
|
|
<226 700 2>,
|
|
<228 440 1>,
|
|
<229 663 1>,
|
|
<230 524 2>,
|
|
<232 612 3>,
|
|
<235 723 5>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tsens2: thermal-sensor@c251000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c251000 0x0 0x1ff>,
|
|
<0x0 0x0c224000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <13>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens3: thermal-sensor@c252000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c252000 0x0 0x1ff>,
|
|
<0x0 0x0c225000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <13>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens0: thermal-sensor@c263000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c263000 0x0 0x1ff>,
|
|
<0x0 0x0c222000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <12>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal-sensor@c265000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c265000 0x0 0x1ff>,
|
|
<0x0 0x0c223000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <12>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-management@c300000 {
|
|
compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
|
|
reg = <0x0 0x0c300000 0x0 0x400>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats";
|
|
reg = <0x0 0x0c3f0000 0x0 0x400>;
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0 0x0c440000 0x0 0x1100>,
|
|
<0x0 0x0c600000 0x0 0x2000000>,
|
|
<0x0 0x0e600000 0x0 0x100000>,
|
|
<0x0 0x0e700000 0x0 0xa0000>,
|
|
<0x0 0x0c40a000 0x0 0x26000>;
|
|
reg-names = "core",
|
|
"chnls",
|
|
"obsrvr",
|
|
"intr",
|
|
"cnfg";
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,sa8775p-tlmm";
|
|
reg = <0x0 0x0f000000 0x0 0x1000000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 149>;
|
|
wakeup-parent = <&pdc>;
|
|
|
|
qup_i2c0_default: qup-i2c0-state {
|
|
pins = "gpio20", "gpio21";
|
|
function = "qup0_se0";
|
|
};
|
|
|
|
qup_i2c1_default: qup-i2c1-state {
|
|
pins = "gpio24", "gpio25";
|
|
function = "qup0_se1";
|
|
};
|
|
|
|
qup_i2c2_default: qup-i2c2-state {
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup0_se2";
|
|
};
|
|
|
|
qup_i2c3_default: qup-i2c3-state {
|
|
pins = "gpio28", "gpio29";
|
|
function = "qup0_se3";
|
|
};
|
|
|
|
qup_i2c4_default: qup-i2c4-state {
|
|
pins = "gpio32", "gpio33";
|
|
function = "qup0_se4";
|
|
};
|
|
|
|
qup_i2c5_default: qup-i2c5-state {
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup0_se5";
|
|
};
|
|
|
|
qup_i2c7_default: qup-i2c7-state {
|
|
pins = "gpio40", "gpio41";
|
|
function = "qup1_se0";
|
|
};
|
|
|
|
qup_i2c8_default: qup-i2c8-state {
|
|
pins = "gpio42", "gpio43";
|
|
function = "qup1_se1";
|
|
};
|
|
|
|
qup_i2c9_default: qup-i2c9-state {
|
|
pins = "gpio46", "gpio47";
|
|
function = "qup1_se2";
|
|
};
|
|
|
|
qup_i2c10_default: qup-i2c10-state {
|
|
pins = "gpio44", "gpio45";
|
|
function = "qup1_se3";
|
|
};
|
|
|
|
qup_i2c11_default: qup-i2c11-state {
|
|
pins = "gpio48", "gpio49";
|
|
function = "qup1_se4";
|
|
};
|
|
|
|
qup_i2c12_default: qup-i2c12-state {
|
|
pins = "gpio52", "gpio53";
|
|
function = "qup1_se5";
|
|
};
|
|
|
|
qup_i2c13_default: qup-i2c13-state {
|
|
pins = "gpio56", "gpio57";
|
|
function = "qup1_se6";
|
|
};
|
|
|
|
qup_i2c14_default: qup-i2c14-state {
|
|
pins = "gpio80", "gpio81";
|
|
function = "qup2_se0";
|
|
};
|
|
|
|
qup_i2c15_default: qup-i2c15-state {
|
|
pins = "gpio84", "gpio85";
|
|
function = "qup2_se1";
|
|
};
|
|
|
|
qup_i2c16_default: qup-i2c16-state {
|
|
pins = "gpio86", "gpio87";
|
|
function = "qup2_se2";
|
|
};
|
|
|
|
qup_i2c17_default: qup-i2c17-state {
|
|
pins = "gpio91", "gpio92";
|
|
function = "qup2_se3";
|
|
};
|
|
|
|
qup_i2c18_default: qup-i2c18-state {
|
|
pins = "gpio95", "gpio96";
|
|
function = "qup2_se4";
|
|
};
|
|
|
|
qup_i2c19_default: qup-i2c19-state {
|
|
pins = "gpio99", "gpio100";
|
|
function = "qup2_se5";
|
|
};
|
|
|
|
qup_i2c20_default: qup-i2c20-state {
|
|
pins = "gpio97", "gpio98";
|
|
function = "qup2_se6";
|
|
};
|
|
|
|
qup_i2c21_default: qup-i2c21-state {
|
|
pins = "gpio13", "gpio14";
|
|
function = "qup3_se0";
|
|
};
|
|
|
|
qup_spi0_default: qup-spi0-state {
|
|
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
|
function = "qup0_se0";
|
|
};
|
|
|
|
qup_spi1_default: qup-spi1-state {
|
|
pins = "gpio24", "gpio25", "gpio26", "gpio27";
|
|
function = "qup0_se1";
|
|
};
|
|
|
|
qup_spi2_default: qup-spi2-state {
|
|
pins = "gpio36", "gpio37", "gpio38", "gpio39";
|
|
function = "qup0_se2";
|
|
};
|
|
|
|
qup_spi3_default: qup-spi3-state {
|
|
pins = "gpio28", "gpio29", "gpio30", "gpio31";
|
|
function = "qup0_se3";
|
|
};
|
|
|
|
qup_spi4_default: qup-spi4-state {
|
|
pins = "gpio32", "gpio33", "gpio34", "gpio35";
|
|
function = "qup0_se4";
|
|
};
|
|
|
|
qup_spi5_default: qup-spi5-state {
|
|
pins = "gpio36", "gpio37", "gpio38", "gpio39";
|
|
function = "qup0_se5";
|
|
};
|
|
|
|
qup_spi7_default: qup-spi7-state {
|
|
pins = "gpio40", "gpio41", "gpio42", "gpio43";
|
|
function = "qup1_se0";
|
|
};
|
|
|
|
qup_spi8_default: qup-spi8-state {
|
|
pins = "gpio42", "gpio43", "gpio40", "gpio41";
|
|
function = "qup1_se1";
|
|
};
|
|
|
|
qup_spi9_default: qup-spi9-state {
|
|
pins = "gpio46", "gpio47", "gpio44", "gpio45";
|
|
function = "qup1_se2";
|
|
};
|
|
|
|
qup_spi10_default: qup-spi10-state {
|
|
pins = "gpio44", "gpio45", "gpio46", "gpio47";
|
|
function = "qup1_se3";
|
|
};
|
|
|
|
qup_spi11_default: qup-spi11-state {
|
|
pins = "gpio48", "gpio49", "gpio50", "gpio51";
|
|
function = "qup1_se4";
|
|
};
|
|
|
|
qup_spi12_default: qup-spi12-state {
|
|
pins = "gpio52", "gpio53", "gpio54", "gpio55";
|
|
function = "qup1_se5";
|
|
};
|
|
|
|
qup_spi14_default: qup-spi14-state {
|
|
pins = "gpio80", "gpio81", "gpio82", "gpio83";
|
|
function = "qup2_se0";
|
|
};
|
|
|
|
qup_spi15_default: qup-spi15-state {
|
|
pins = "gpio84", "gpio85", "gpio99", "gpio100";
|
|
function = "qup2_se1";
|
|
};
|
|
|
|
qup_spi16_default: qup-spi16-state {
|
|
pins = "gpio86", "gpio87", "gpio88", "gpio89";
|
|
function = "qup2_se2";
|
|
};
|
|
|
|
qup_spi17_default: qup-spi17-state {
|
|
pins = "gpio91", "gpio92", "gpio93", "gpio94";
|
|
function = "qup2_se3";
|
|
};
|
|
|
|
qup_spi18_default: qup-spi18-state {
|
|
pins = "gpio95", "gpio96", "gpio97", "gpio98";
|
|
function = "qup2_se4";
|
|
};
|
|
|
|
qup_spi19_default: qup-spi19-state {
|
|
pins = "gpio99", "gpio100", "gpio84", "gpio85";
|
|
function = "qup2_se5";
|
|
};
|
|
|
|
qup_spi20_default: qup-spi20-state {
|
|
pins = "gpio97", "gpio98", "gpio95", "gpio96";
|
|
function = "qup2_se6";
|
|
};
|
|
|
|
qup_spi21_default: qup-spi21-state {
|
|
pins = "gpio13", "gpio14", "gpio15", "gpio16";
|
|
function = "qup3_se0";
|
|
};
|
|
|
|
qup_uart0_default: qup-uart0-state {
|
|
qup_uart0_cts: qup-uart0-cts-pins {
|
|
pins = "gpio20";
|
|
function = "qup0_se0";
|
|
};
|
|
|
|
qup_uart0_rts: qup-uart0-rts-pins {
|
|
pins = "gpio21";
|
|
function = "qup0_se0";
|
|
};
|
|
|
|
qup_uart0_tx: qup-uart0-tx-pins {
|
|
pins = "gpio22";
|
|
function = "qup0_se0";
|
|
};
|
|
|
|
qup_uart0_rx: qup-uart0-rx-pins {
|
|
pins = "gpio23";
|
|
function = "qup0_se0";
|
|
};
|
|
};
|
|
|
|
qup_uart1_default: qup-uart1-state {
|
|
qup_uart1_cts: qup-uart1-cts-pins {
|
|
pins = "gpio24";
|
|
function = "qup0_se1";
|
|
};
|
|
|
|
qup_uart1_rts: qup-uart1-rts-pins {
|
|
pins = "gpio25";
|
|
function = "qup0_se1";
|
|
};
|
|
|
|
qup_uart1_tx: qup-uart1-tx-pins {
|
|
pins = "gpio26";
|
|
function = "qup0_se1";
|
|
};
|
|
|
|
qup_uart1_rx: qup-uart1-rx-pins {
|
|
pins = "gpio27";
|
|
function = "qup0_se1";
|
|
};
|
|
};
|
|
|
|
qup_uart2_default: qup-uart2-state {
|
|
qup_uart2_cts: qup-uart2-cts-pins {
|
|
pins = "gpio36";
|
|
function = "qup0_se2";
|
|
};
|
|
|
|
qup_uart2_rts: qup-uart2-rts-pins {
|
|
pins = "gpio37";
|
|
function = "qup0_se2";
|
|
};
|
|
|
|
qup_uart2_tx: qup-uart2-tx-pins {
|
|
pins = "gpio38";
|
|
function = "qup0_se2";
|
|
};
|
|
|
|
qup_uart2_rx: qup-uart2-rx-pins {
|
|
pins = "gpio39";
|
|
function = "qup0_se2";
|
|
};
|
|
};
|
|
|
|
qup_uart3_default: qup-uart3-state {
|
|
qup_uart3_cts: qup-uart3-cts-pins {
|
|
pins = "gpio28";
|
|
function = "qup0_se3";
|
|
};
|
|
|
|
qup_uart3_rts: qup-uart3-rts-pins {
|
|
pins = "gpio29";
|
|
function = "qup0_se3";
|
|
};
|
|
|
|
qup_uart3_tx: qup-uart3-tx-pins {
|
|
pins = "gpio30";
|
|
function = "qup0_se3";
|
|
};
|
|
|
|
qup_uart3_rx: qup-uart3-rx-pins {
|
|
pins = "gpio31";
|
|
function = "qup0_se3";
|
|
};
|
|
};
|
|
|
|
qup_uart4_default: qup-uart4-state {
|
|
qup_uart4_cts: qup-uart4-cts-pins {
|
|
pins = "gpio32";
|
|
function = "qup0_se4";
|
|
};
|
|
|
|
qup_uart4_rts: qup-uart4-rts-pins {
|
|
pins = "gpio33";
|
|
function = "qup0_se4";
|
|
};
|
|
|
|
qup_uart4_tx: qup-uart4-tx-pins {
|
|
pins = "gpio34";
|
|
function = "qup0_se4";
|
|
};
|
|
|
|
qup_uart4_rx: qup-uart4-rx-pins {
|
|
pins = "gpio35";
|
|
function = "qup0_se4";
|
|
};
|
|
};
|
|
|
|
qup_uart5_default: qup-uart5-state {
|
|
qup_uart5_cts: qup-uart5-cts-pins {
|
|
pins = "gpio36";
|
|
function = "qup0_se5";
|
|
};
|
|
|
|
qup_uart5_rts: qup-uart5-rts-pins {
|
|
pins = "gpio37";
|
|
function = "qup0_se5";
|
|
};
|
|
|
|
qup_uart5_tx: qup-uart5-tx-pins {
|
|
pins = "gpio38";
|
|
function = "qup0_se5";
|
|
};
|
|
|
|
qup_uart5_rx: qup-uart5-rx-pins {
|
|
pins = "gpio39";
|
|
function = "qup0_se5";
|
|
};
|
|
};
|
|
|
|
qup_uart7_default: qup-uart7-state {
|
|
qup_uart7_cts: qup-uart7-cts-pins {
|
|
pins = "gpio40";
|
|
function = "qup1_se0";
|
|
};
|
|
|
|
qup_uart7_rts: qup-uart7-rts-pins {
|
|
pins = "gpio41";
|
|
function = "qup1_se0";
|
|
};
|
|
|
|
qup_uart7_tx: qup-uart7-tx-pins {
|
|
pins = "gpio42";
|
|
function = "qup1_se0";
|
|
};
|
|
|
|
qup_uart7_rx: qup-uart7-rx-pins {
|
|
pins = "gpio43";
|
|
function = "qup1_se0";
|
|
};
|
|
};
|
|
|
|
qup_uart8_default: qup-uart8-state {
|
|
qup_uart8_cts: qup-uart8-cts-pins {
|
|
pins = "gpio42";
|
|
function = "qup1_se1";
|
|
};
|
|
|
|
qup_uart8_rts: qup-uart8-rts-pins {
|
|
pins = "gpio43";
|
|
function = "qup1_se1";
|
|
};
|
|
|
|
qup_uart8_tx: qup-uart8-tx-pins {
|
|
pins = "gpio40";
|
|
function = "qup1_se1";
|
|
};
|
|
|
|
qup_uart8_rx: qup-uart8-rx-pins {
|
|
pins = "gpio41";
|
|
function = "qup1_se1";
|
|
};
|
|
};
|
|
|
|
qup_uart9_default: qup-uart9-state {
|
|
qup_uart9_cts: qup-uart9-cts-pins {
|
|
pins = "gpio46";
|
|
function = "qup1_se2";
|
|
};
|
|
|
|
qup_uart9_rts: qup-uart9-rts-pins {
|
|
pins = "gpio47";
|
|
function = "qup1_se2";
|
|
};
|
|
|
|
qup_uart9_tx: qup-uart9-tx-pins {
|
|
pins = "gpio44";
|
|
function = "qup1_se2";
|
|
};
|
|
|
|
qup_uart9_rx: qup-uart9-rx-pins {
|
|
pins = "gpio45";
|
|
function = "qup1_se2";
|
|
};
|
|
};
|
|
|
|
qup_uart10_default: qup-uart10-state {
|
|
pins = "gpio46", "gpio47";
|
|
function = "qup1_se3";
|
|
};
|
|
|
|
qup_uart11_default: qup-uart11-state {
|
|
qup_uart11_cts: qup-uart11-cts-pins {
|
|
pins = "gpio48";
|
|
function = "qup1_se4";
|
|
};
|
|
|
|
qup_uart11_rts: qup-uart11-rts-pins {
|
|
pins = "gpio49";
|
|
function = "qup1_se4";
|
|
};
|
|
|
|
qup_uart11_tx: qup-uart11-tx-pins {
|
|
pins = "gpio50";
|
|
function = "qup1_se4";
|
|
};
|
|
|
|
qup_uart11_rx: qup-uart11-rx-pins {
|
|
pins = "gpio51";
|
|
function = "qup1_se4";
|
|
};
|
|
};
|
|
|
|
qup_uart12_default: qup-uart12-state {
|
|
qup_uart12_cts: qup-uart12-cts-pins {
|
|
pins = "gpio52";
|
|
function = "qup1_se5";
|
|
};
|
|
|
|
qup_uart12_rts: qup-uart12-rts-pins {
|
|
pins = "gpio53";
|
|
function = "qup1_se5";
|
|
};
|
|
|
|
qup_uart12_tx: qup-uart12-tx-pins {
|
|
pins = "gpio54";
|
|
function = "qup1_se5";
|
|
};
|
|
|
|
qup_uart12_rx: qup-uart12-rx-pins {
|
|
pins = "gpio55";
|
|
function = "qup1_se5";
|
|
};
|
|
};
|
|
|
|
qup_uart14_default: qup-uart14-state {
|
|
qup_uart14_cts: qup-uart14-cts-pins {
|
|
pins = "gpio80";
|
|
function = "qup2_se0";
|
|
};
|
|
|
|
qup_uart14_rts: qup-uart14-rts-pins {
|
|
pins = "gpio81";
|
|
function = "qup2_se0";
|
|
};
|
|
|
|
qup_uart14_tx: qup-uart14-tx-pins {
|
|
pins = "gpio82";
|
|
function = "qup2_se0";
|
|
};
|
|
|
|
qup_uart14_rx: qup-uart14-rx-pins {
|
|
pins = "gpio83";
|
|
function = "qup2_se0";
|
|
};
|
|
};
|
|
|
|
qup_uart15_default: qup-uart15-state {
|
|
qup_uart15_cts: qup-uart15-cts-pins {
|
|
pins = "gpio84";
|
|
function = "qup2_se1";
|
|
};
|
|
|
|
qup_uart15_rts: qup-uart15-rts-pins {
|
|
pins = "gpio85";
|
|
function = "qup2_se1";
|
|
};
|
|
|
|
qup_uart15_tx: qup-uart15-tx-pins {
|
|
pins = "gpio99";
|
|
function = "qup2_se1";
|
|
};
|
|
|
|
qup_uart15_rx: qup-uart15-rx-pins {
|
|
pins = "gpio100";
|
|
function = "qup2_se1";
|
|
};
|
|
};
|
|
|
|
qup_uart16_default: qup-uart16-state {
|
|
qup_uart16_cts: qup-uart16-cts-pins {
|
|
pins = "gpio86";
|
|
function = "qup2_se2";
|
|
};
|
|
|
|
qup_uart16_rts: qup-uart16-rts-pins {
|
|
pins = "gpio87";
|
|
function = "qup2_se2";
|
|
};
|
|
|
|
qup_uart16_tx: qup-uart16-tx-pins {
|
|
pins = "gpio88";
|
|
function = "qup2_se2";
|
|
};
|
|
|
|
qup_uart16_rx: qup-uart16-rx-pins {
|
|
pins = "gpio89";
|
|
function = "qup2_se2";
|
|
};
|
|
};
|
|
|
|
qup_uart17_default: qup-uart17-state {
|
|
qup_uart17_cts: qup-uart17-cts-pins {
|
|
pins = "gpio91";
|
|
function = "qup2_se3";
|
|
};
|
|
|
|
qup_uart17_rts: qup0-uart17-rts-pins {
|
|
pins = "gpio92";
|
|
function = "qup2_se3";
|
|
};
|
|
|
|
qup_uart17_tx: qup0-uart17-tx-pins {
|
|
pins = "gpio93";
|
|
function = "qup2_se3";
|
|
};
|
|
|
|
qup_uart17_rx: qup0-uart17-rx-pins {
|
|
pins = "gpio94";
|
|
function = "qup2_se3";
|
|
};
|
|
};
|
|
|
|
qup_uart18_default: qup-uart18-state {
|
|
qup_uart18_cts: qup-uart18-cts-pins {
|
|
pins = "gpio95";
|
|
function = "qup2_se4";
|
|
};
|
|
|
|
qup_uart18_rts: qup-uart18-rts-pins {
|
|
pins = "gpio96";
|
|
function = "qup2_se4";
|
|
};
|
|
|
|
qup_uart18_tx: qup-uart18-tx-pins {
|
|
pins = "gpio97";
|
|
function = "qup2_se4";
|
|
};
|
|
|
|
qup_uart18_rx: qup-uart18-rx-pins {
|
|
pins = "gpio98";
|
|
function = "qup2_se4";
|
|
};
|
|
};
|
|
|
|
qup_uart19_default: qup-uart19-state {
|
|
qup_uart19_cts: qup-uart19-cts-pins {
|
|
pins = "gpio99";
|
|
function = "qup2_se5";
|
|
};
|
|
|
|
qup_uart19_rts: qup-uart19-rts-pins {
|
|
pins = "gpio100";
|
|
function = "qup2_se5";
|
|
};
|
|
|
|
qup_uart19_tx: qup-uart19-tx-pins {
|
|
pins = "gpio84";
|
|
function = "qup2_se5";
|
|
};
|
|
|
|
qup_uart19_rx: qup-uart19-rx-pins {
|
|
pins = "gpio85";
|
|
function = "qup2_se5";
|
|
};
|
|
};
|
|
|
|
qup_uart20_default: qup-uart20-state {
|
|
qup_uart20_cts: qup-uart20-cts-pins {
|
|
pins = "gpio97";
|
|
function = "qup2_se6";
|
|
};
|
|
|
|
qup_uart20_rts: qup-uart20-rts-pins {
|
|
pins = "gpio98";
|
|
function = "qup2_se6";
|
|
};
|
|
|
|
qup_uart20_tx: qup-uart20-tx-pins {
|
|
pins = "gpio95";
|
|
function = "qup2_se6";
|
|
};
|
|
|
|
qup_uart20_rx: qup-uart20-rx-pins {
|
|
pins = "gpio96";
|
|
function = "qup2_se6";
|
|
};
|
|
};
|
|
|
|
qup_uart21_default: qup-uart21-state {
|
|
qup_uart21_cts: qup-uart21-cts-pins {
|
|
pins = "gpio13";
|
|
function = "qup3_se0";
|
|
};
|
|
|
|
qup_uart21_rts: qup-uart21-rts-pins {
|
|
pins = "gpio14";
|
|
function = "qup3_se0";
|
|
};
|
|
|
|
qup_uart21_tx: qup-uart21-tx-pins {
|
|
pins = "gpio15";
|
|
function = "qup3_se0";
|
|
};
|
|
|
|
qup_uart21_rx: qup-uart21-rx-pins {
|
|
pins = "gpio16";
|
|
function = "qup3_se0";
|
|
};
|
|
};
|
|
};
|
|
|
|
sram: sram@146d8000 {
|
|
compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
|
|
reg = <0x0 0x146d8000 0x0 0x1000>;
|
|
ranges = <0x0 0x0 0x146d8000 0x1000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pil-reloc@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15000000 0x0 0x100000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
dma-coherent;
|
|
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pcie_smmu: iommu@15200000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15200000 0x0 0x80000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
dma-coherent;
|
|
|
|
interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
};
|
|
|
|
watchdog@17c10000 {
|
|
compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
|
|
reg = <0x0 0x17c10000 0x0 0x1000>;
|
|
clocks = <&sleep_clk>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
memtimer: timer@17c20000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0 0x17c20000 0x0 0x1000>;
|
|
ranges = <0x0 0x0 0x0 0x20000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
frame@17c21000 {
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <0>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
reg = <0x17c23000 0x1000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
reg = <0x17c25000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
reg = <0x17c27000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
reg = <0x17c29000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
reg = <0x17c2b000 0x1000>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
reg = <0x17c2d000 0x1000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x18200000 0x0 0x10000>,
|
|
<0x0 0x18210000 0x0 0x10000>,
|
|
<0x0 0x18220000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 0>;
|
|
label = "apps_rsc";
|
|
power-domains = <&system_pd>;
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sa8775p-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board_clk>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sa8775p-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp-0 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp-1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp-4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp-5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp-6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp-7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp-8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp-9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
epss_l3_cl0: interconnect@18590000 {
|
|
compatible = "qcom,sa8775p-epss-l3",
|
|
"qcom,epss-l3";
|
|
reg = <0x0 0x18590000 0x0 0x1000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18591000 {
|
|
compatible = "qcom,sa8775p-cpufreq-epss",
|
|
"qcom,cpufreq-epss";
|
|
reg = <0x0 0x18591000 0x0 0x1000>,
|
|
<0x0 0x18593000 0x0 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
|
|
epss_l3_cl1: interconnect@18592000 {
|
|
compatible = "qcom,sa8775p-epss-l3",
|
|
"qcom,epss-l3";
|
|
reg = <0x0 0x18592000 0x0 0x1000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
remoteproc_gpdsp0: remoteproc@20c00000 {
|
|
compatible = "qcom,sa8775p-gpdsp0-pas";
|
|
reg = <0x0 0x20c00000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_gpdsp0_in 0 0>,
|
|
<&smp2p_gpdsp0_in 1 0>,
|
|
<&smp2p_gpdsp0_in 2 0>,
|
|
<&smp2p_gpdsp0_in 3 0>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MXC>;
|
|
power-domain-names = "cx", "mxc";
|
|
|
|
interconnects = <&gpdsp_anoc MASTER_DSP0 0
|
|
&config_noc SLAVE_CLK_CTL 0>;
|
|
|
|
memory-region = <&pil_gdsp0_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_gpdsp0_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_GPDSP0
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "gpdsp0";
|
|
qcom,remote-pid = <17>;
|
|
};
|
|
};
|
|
|
|
remoteproc_gpdsp1: remoteproc@21c00000 {
|
|
compatible = "qcom,sa8775p-gpdsp1-pas";
|
|
reg = <0x0 0x21c00000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_gpdsp1_in 0 0>,
|
|
<&smp2p_gpdsp1_in 1 0>,
|
|
<&smp2p_gpdsp1_in 2 0>,
|
|
<&smp2p_gpdsp1_in 3 0>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MXC>;
|
|
power-domain-names = "cx", "mxc";
|
|
|
|
interconnects = <&gpdsp_anoc MASTER_DSP1 0
|
|
&config_noc SLAVE_CLK_CTL 0>;
|
|
|
|
memory-region = <&pil_gdsp1_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_gpdsp1_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_GPDSP1
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "gpdsp1";
|
|
qcom,remote-pid = <18>;
|
|
};
|
|
};
|
|
|
|
dispcc1: clock-controller@22100000 {
|
|
compatible = "qcom,sa8775p-dispcc1";
|
|
reg = <0x0 0x22100000 0x0 0x20000>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<0>, <0>, <0>, <0>,
|
|
<0>, <0>, <0>, <0>;
|
|
power-domains = <&rpmhpd SA8775P_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet1: ethernet@23000000 {
|
|
compatible = "qcom,sa8775p-ethqos";
|
|
reg = <0x0 0x23000000 0x0 0x10000>,
|
|
<0x0 0x23016000 0x0 0x100>;
|
|
reg-names = "stmmaceth", "rgmii";
|
|
|
|
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "sfty";
|
|
|
|
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
|
|
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
|
|
<&gcc GCC_EMAC1_PTP_CLK>,
|
|
<&gcc GCC_EMAC1_PHY_AUX_CLK>;
|
|
clock-names = "stmmaceth",
|
|
"pclk",
|
|
"ptp_ref",
|
|
"phyaux";
|
|
|
|
interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "mac-mem", "cpu-mac";
|
|
|
|
power-domains = <&gcc EMAC1_GDSC>;
|
|
|
|
phys = <&serdes1>;
|
|
phy-names = "serdes";
|
|
|
|
iommus = <&apps_smmu 0x140 0xf>;
|
|
dma-coherent;
|
|
|
|
snps,tso;
|
|
snps,pbl = <32>;
|
|
rx-fifo-depth = <16384>;
|
|
tx-fifo-depth = <16384>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet0: ethernet@23040000 {
|
|
compatible = "qcom,sa8775p-ethqos";
|
|
reg = <0x0 0x23040000 0x0 0x10000>,
|
|
<0x0 0x23056000 0x0 0x100>;
|
|
reg-names = "stmmaceth", "rgmii";
|
|
|
|
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "sfty";
|
|
|
|
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
|
|
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
|
|
<&gcc GCC_EMAC0_PTP_CLK>,
|
|
<&gcc GCC_EMAC0_PHY_AUX_CLK>;
|
|
clock-names = "stmmaceth",
|
|
"pclk",
|
|
"ptp_ref",
|
|
"phyaux";
|
|
|
|
interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "mac-mem", "cpu-mac";
|
|
|
|
power-domains = <&gcc EMAC0_GDSC>;
|
|
|
|
phys = <&serdes0>;
|
|
phy-names = "serdes";
|
|
|
|
iommus = <&apps_smmu 0x120 0xf>;
|
|
dma-coherent;
|
|
|
|
snps,tso;
|
|
snps,pbl = <32>;
|
|
rx-fifo-depth = <16384>;
|
|
tx-fifo-depth = <16384>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
remoteproc_cdsp0: remoteproc@26300000 {
|
|
compatible = "qcom,sa8775p-cdsp0-pas";
|
|
reg = <0x0 0x26300000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MXC>,
|
|
<&rpmhpd RPMHPD_NSP0>;
|
|
power-domain-names = "cx", "mxc", "nsp";
|
|
|
|
interconnects = <&nspa_noc MASTER_CDSP_PROC 0
|
|
&mc_virt SLAVE_EBI1 0>;
|
|
|
|
memory-region = <&pil_cdsp0_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_cdsp0_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "cdsp";
|
|
qcom,remote-pid = <5>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "cdsp";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@1 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <1>;
|
|
iommus = <&apps_smmu 0x2141 0x04a0>,
|
|
<&apps_smmu 0x2181 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@2 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <2>;
|
|
iommus = <&apps_smmu 0x2142 0x04a0>,
|
|
<&apps_smmu 0x2182 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x2143 0x04a0>,
|
|
<&apps_smmu 0x2183 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
iommus = <&apps_smmu 0x2144 0x04a0>,
|
|
<&apps_smmu 0x2184 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
iommus = <&apps_smmu 0x2145 0x04a0>,
|
|
<&apps_smmu 0x2185 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@6 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <6>;
|
|
iommus = <&apps_smmu 0x2146 0x04a0>,
|
|
<&apps_smmu 0x2186 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@7 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <7>;
|
|
iommus = <&apps_smmu 0x2147 0x04a0>,
|
|
<&apps_smmu 0x2187 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@8 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <8>;
|
|
iommus = <&apps_smmu 0x2148 0x04a0>,
|
|
<&apps_smmu 0x2188 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@9 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <9>;
|
|
iommus = <&apps_smmu 0x2149 0x04a0>,
|
|
<&apps_smmu 0x2189 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@11 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <11>;
|
|
iommus = <&apps_smmu 0x214b 0x04a0>,
|
|
<&apps_smmu 0x218b 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc_cdsp1: remoteproc@2a300000 {
|
|
compatible = "qcom,sa8775p-cdsp1-pas";
|
|
reg = <0x0 0x2A300000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MXC>,
|
|
<&rpmhpd RPMHPD_NSP1>;
|
|
power-domain-names = "cx", "mxc", "nsp";
|
|
|
|
interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
|
|
&mc_virt SLAVE_EBI1 0>;
|
|
|
|
memory-region = <&pil_cdsp1_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_cdsp1_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_NSP1
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "cdsp";
|
|
qcom,remote-pid = <12>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "cdsp1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@1 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <1>;
|
|
iommus = <&apps_smmu 0x2941 0x04a0>,
|
|
<&apps_smmu 0x2981 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@2 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <2>;
|
|
iommus = <&apps_smmu 0x2942 0x04a0>,
|
|
<&apps_smmu 0x2982 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x2943 0x04a0>,
|
|
<&apps_smmu 0x2983 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
iommus = <&apps_smmu 0x2944 0x04a0>,
|
|
<&apps_smmu 0x2984 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
iommus = <&apps_smmu 0x2945 0x04a0>,
|
|
<&apps_smmu 0x2985 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@6 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <6>;
|
|
iommus = <&apps_smmu 0x2946 0x04a0>,
|
|
<&apps_smmu 0x2986 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@7 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <7>;
|
|
iommus = <&apps_smmu 0x2947 0x04a0>,
|
|
<&apps_smmu 0x2987 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@8 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <8>;
|
|
iommus = <&apps_smmu 0x2948 0x04a0>,
|
|
<&apps_smmu 0x2988 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@9 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <9>;
|
|
iommus = <&apps_smmu 0x2949 0x04a0>,
|
|
<&apps_smmu 0x2989 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@10 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <10>;
|
|
iommus = <&apps_smmu 0x294a 0x04a0>,
|
|
<&apps_smmu 0x298a 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@11 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <11>;
|
|
iommus = <&apps_smmu 0x294b 0x04a0>,
|
|
<&apps_smmu 0x298b 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@12 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <12>;
|
|
iommus = <&apps_smmu 0x294c 0x04a0>,
|
|
<&apps_smmu 0x298c 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@13 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <13>;
|
|
iommus = <&apps_smmu 0x294d 0x04a0>,
|
|
<&apps_smmu 0x298d 0x0400>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc_adsp: remoteproc@30000000 {
|
|
compatible = "qcom,sa8775p-adsp-pas";
|
|
reg = <0x0 0x30000000 0x0 0x100>;
|
|
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover",
|
|
"stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_LCX>,
|
|
<&rpmhpd RPMHPD_LMX>;
|
|
power-domain-names = "lcx", "lmx";
|
|
|
|
interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_adsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
remoteproc_adsp_glink: glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "lpass";
|
|
qcom,remote-pid = <2>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "adsp";
|
|
memory-region = <&adsp_rpc_remote_heap_mem>;
|
|
qcom,vmids = <QCOM_SCM_VMID_LPASS
|
|
QCOM_SCM_VMID_ADSP_HEAP>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x3003 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
iommus = <&apps_smmu 0x3004 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
iommus = <&apps_smmu 0x3005 0x0>;
|
|
qcom,nsessions = <5>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
aoss-0-thermal {
|
|
thermal-sensors = <&tsens0 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-2-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens0 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
audio-thermal {
|
|
thermal-sensors = <&tsens0 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camss-0-thermal {
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie-0-thermal {
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-0-thermal {
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-1-thermal {
|
|
thermal-sensors = <&tsens1 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-3-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-4-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-5-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-thermal {
|
|
thermal-sensors = <&tsens1 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camss-1-thermal {
|
|
thermal-sensors = <&tsens1 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie-1-thermal {
|
|
thermal-sensors = <&tsens1 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-1-thermal {
|
|
thermal-sensors = <&tsens1 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-2-thermal {
|
|
thermal-sensors = <&tsens2 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddrss-0-thermal {
|
|
thermal-sensors = <&tsens2 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-0-thermal {
|
|
thermal-sensors = <&tsens2 12>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-3-thermal {
|
|
thermal-sensors = <&tsens3 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens3 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddrss-1-thermal {
|
|
thermal-sensors = <&tsens3 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-1-thermal {
|
|
thermal-sensors = <&tsens3 12>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
pcie0: pcie@1c00000 {
|
|
compatible = "qcom,pcie-sa8775p";
|
|
reg = <0x0 0x01c00000 0x0 0x3000>,
|
|
<0x0 0x40000000 0x0 0xf20>,
|
|
<0x0 0x40000f20 0x0 0xa8>,
|
|
<0x0 0x40001000 0x0 0x4000>,
|
|
<0x0 0x40100000 0x0 0x100000>,
|
|
<0x0 0x01c03000 0x0 0x1000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
dma-coherent;
|
|
|
|
linux,pci-domain = <0>;
|
|
num-lanes = <2>;
|
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
|
|
<0x100 &pcie_smmu 0x0001 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>;
|
|
reset-names = "pci";
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
|
|
pcieport0: pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie0_ep: pcie-ep@1c00000 {
|
|
compatible = "qcom,sa8775p-pcie-ep";
|
|
reg = <0x0 0x01c00000 0x0 0x3000>,
|
|
<0x0 0x40000000 0x0 0xf20>,
|
|
<0x0 0x40000f20 0x0 0xa8>,
|
|
<0x0 0x40001000 0x0 0x4000>,
|
|
<0x0 0x40200000 0x0 0x1fe00000>,
|
|
<0x0 0x01c03000 0x0 0x1000>,
|
|
<0x0 0x40005000 0x0 0x2000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
|
|
"mmio", "dma";
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "global", "doorbell", "dma";
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
dma-coherent;
|
|
iommus = <&pcie_smmu 0x0000 0x7f>;
|
|
resets = <&gcc GCC_PCIE_0_BCR>;
|
|
reset-names = "core";
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
|
|
num-lanes = <2>;
|
|
linux,pci-domain = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0_phy: phy@1c04000 {
|
|
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
|
|
reg = <0x0 0x1c04000 0x0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
|
|
<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
|
|
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
|
|
"pipediv2", "phy_aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@1c10000 {
|
|
compatible = "qcom,pcie-sa8775p";
|
|
reg = <0x0 0x01c10000 0x0 0x3000>,
|
|
<0x0 0x60000000 0x0 0xf20>,
|
|
<0x0 0x60000f20 0x0 0xa8>,
|
|
<0x0 0x60001000 0x0 0x4000>,
|
|
<0x0 0x60100000 0x0 0x100000>,
|
|
<0x0 0x01c13000 0x0 0x1000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
dma-coherent;
|
|
|
|
linux,pci-domain = <1>;
|
|
num-lanes = <4>;
|
|
|
|
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
|
|
<0x100 &pcie_smmu 0x0081 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>;
|
|
reset-names = "pci";
|
|
power-domains = <&gcc PCIE_1_GDSC>;
|
|
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie1_ep: pcie-ep@1c10000 {
|
|
compatible = "qcom,sa8775p-pcie-ep";
|
|
reg = <0x0 0x01c10000 0x0 0x3000>,
|
|
<0x0 0x60000000 0x0 0xf20>,
|
|
<0x0 0x60000f20 0x0 0xa8>,
|
|
<0x0 0x60001000 0x0 0x4000>,
|
|
<0x0 0x60200000 0x0 0x1fe00000>,
|
|
<0x0 0x01c13000 0x0 0x1000>,
|
|
<0x0 0x60005000 0x0 0x2000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
|
|
"mmio", "dma";
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "global", "doorbell", "dma";
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
dma-coherent;
|
|
iommus = <&pcie_smmu 0x80 0x7f>;
|
|
resets = <&gcc GCC_PCIE_1_BCR>;
|
|
reset-names = "core";
|
|
power-domains = <&gcc PCIE_1_GDSC>;
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
|
|
num-lanes = <4>;
|
|
linux,pci-domain = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1_phy: phy@1c14000 {
|
|
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
|
|
reg = <0x0 0x1c14000 0x0 0x4000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
|
|
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
|
|
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
|
|
"pipediv2", "phy_aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|