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8140d10568
Remove eMMC node for rdp433, since rdp433 default boot mode is norplusnand Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20250306113357.126602-4-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
164 lines
2.8 KiB
Plaintext
164 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ9574 RDP433 board device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "ipq9574-rdp-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
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compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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};
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&pcie1_phy {
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status = "okay";
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};
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&pcie1 {
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pinctrl-0 = <&pcie1_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie2_phy {
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status = "okay";
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};
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&pcie2 {
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pinctrl-0 = <&pcie2_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie3_phy {
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status = "okay";
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};
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&pcie3 {
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pinctrl-0 = <&pcie3_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&tlmm {
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pcie1_default: pcie1-default-state {
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clkreq-n-pins {
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pins = "gpio25";
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function = "pcie1_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio26";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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output-low;
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};
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wake-n-pins {
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pins = "gpio27";
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function = "pcie1_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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pcie2_default: pcie2-default-state {
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clkreq-n-pins {
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pins = "gpio28";
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function = "pcie2_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio29";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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output-low;
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};
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wake-n-pins {
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pins = "gpio30";
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function = "pcie2_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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pcie3_default: pcie3-default-state {
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clkreq-n-pins {
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pins = "gpio31";
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function = "pcie3_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio32";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-up;
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output-low;
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};
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wake-n-pins {
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pins = "gpio33";
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function = "pcie3_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3", "gpio6", "gpio7",
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"gpio8", "gpio9";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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rclk-pins {
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pins = "gpio10";
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function = "sdc_rclk";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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};
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