mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 14:13:39 +00:00
ab7f31a383
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250416122538.2953658-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1245 lines
29 KiB
Plaintext
1245 lines
29 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ5424 device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
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#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
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#include <dt-bindings/interconnect/qcom,ipq5424.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x100>;
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next-level-cache = <&l2_100>;
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l2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x200>;
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next-level-cache = <&l2_200>;
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l2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x300>;
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next-level-cache = <&l2_300>;
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l2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq5424", "qcom,scm";
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qcom,dload-mode = <&tcsr 0x25100>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-dsu {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bootloader@8a200000 {
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reg = <0x0 0x8a200000 0x0 0x400000>;
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no-map;
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};
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tz@8a600000 {
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reg = <0x0 0x8a600000 0x0 0x200000>;
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no-map;
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};
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smem@8a800000 {
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compatible = "qcom,smem";
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reg = <0x0 0x8a800000 0x0 0x32000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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pcie0_phy: phy@84000 {
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compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
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"qcom,ipq9574-qmp-gen3x1-pcie-phy";
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reg = <0x0 0x00084000 0x0 0x1000>;
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clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>,
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<&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"pipe";
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assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
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assigned-clock-rates = <20000000>;
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <0>;
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clock-output-names = "gcc_pcie0_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie1_phy: phy@8c000 {
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compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
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"qcom,ipq9574-qmp-gen3x1-pcie-phy";
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reg = <0x0 0x0008c000 0x0 0x1000>;
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clocks = <&gcc GCC_PCIE1_AUX_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>,
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<&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"pipe";
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assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
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assigned-clock-rates = <20000000>;
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <0>;
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clock-output-names = "gcc_pcie1_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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efuse@a4000 {
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compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
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reg = <0 0x000a4000 0 0x741>;
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#address-cells = <1>;
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#size-cells = <1>;
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tsens_sens9_off: s9@3dc {
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reg = <0x3dc 0x1>;
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bits = <4 4>;
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};
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tsens_sens10_off: s10@3dd {
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reg = <0x3dd 0x1>;
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bits = <0 4>;
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};
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tsens_sens11_off: s11@3dd {
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reg = <0x3dd 0x1>;
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bits = <4 4>;
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};
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tsens_sens12_off: s12@3de {
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reg = <0x3de 0x1>;
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bits = <0 4>;
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};
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tsens_sens13_off: s13@3de {
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reg = <0x3de 0x1>;
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bits = <4 4>;
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};
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tsens_sens14_off: s14@3e5 {
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reg = <0x3e5 0x2>;
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bits = <7 4>;
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};
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tsens_sens15_off: s15@3e6 {
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reg = <0x3e6 0x1>;
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bits = <3 4>;
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};
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tsens_mode: mode@419 {
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reg = <0x419 0x1>;
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bits = <0 3>;
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};
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tsens_base0: base0@419 {
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reg = <0x419 0x2>;
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bits = <3 10>;
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};
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tsens_base1: base1@41a {
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reg = <0x41a 0x2>;
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bits = <5 10>;
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};
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};
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pcie2_phy: phy@f4000 {
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compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
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"qcom,ipq9574-qmp-gen3x2-pcie-phy";
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reg = <0x0 0x000f4000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE2_AUX_CLK>,
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<&gcc GCC_PCIE2_AHB_CLK>,
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<&gcc GCC_PCIE2_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"pipe";
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assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
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assigned-clock-rates = <20000000>;
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resets = <&gcc GCC_PCIE2_PHY_BCR>,
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<&gcc GCC_PCIE2PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <0>;
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clock-output-names = "gcc_pcie2_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie3_phy: phy@fc000 {
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compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
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"qcom,ipq9574-qmp-gen3x2-pcie-phy";
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reg = <0x0 0x000fc000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE3_AUX_CLK>,
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<&gcc GCC_PCIE3_AHB_CLK>,
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<&gcc GCC_PCIE3_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"pipe";
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assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
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assigned-clock-rates = <20000000>;
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resets = <&gcc GCC_PCIE3_PHY_BCR>,
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<&gcc GCC_PCIE3PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <0>;
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clock-output-names = "gcc_pcie3_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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tsens: thermal-sensor@4a9000 {
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compatible = "qcom,ipq5424-tsens";
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reg = <0 0x004a9000 0 0x1000>,
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<0 0x004a8000 0 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "combined";
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nvmem-cells = <&tsens_mode>,
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<&tsens_base0>,
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<&tsens_base1>,
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<&tsens_sens9_off>,
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<&tsens_sens10_off>,
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<&tsens_sens11_off>,
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<&tsens_sens12_off>,
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<&tsens_sens13_off>,
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<&tsens_sens14_off>,
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<&tsens_sens15_off>;
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nvmem-cell-names = "mode",
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"base0",
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"base1",
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"tsens_sens9_off",
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"tsens_sens10_off",
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"tsens_sens11_off",
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"tsens_sens12_off",
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"tsens_sens13_off",
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"tsens_sens14_off",
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"tsens_sens15_off";
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#qcom,sensors = <7>;
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#thermal-sensor-cells = <1>;
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};
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rng: rng@4c3000 {
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compatible = "qcom,ipq5424-trng", "qcom,trng";
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reg = <0 0x004c3000 0 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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system-cache-controller@800000 {
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compatible = "qcom,ipq5424-llcc";
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reg = <0 0x00800000 0 0x200000>;
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reg-names = "llcc0_base";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5424-tlmm";
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reg = <0 0x01000000 0 0x300000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 50>;
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interrupt-controller;
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#interrupt-cells = <2>;
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uart1_pins: uart1-state {
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pins = "gpio43", "gpio44";
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function = "uart1";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,ipq5424-gcc";
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reg = <0 0x01800000 0 0x40000>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<&pcie0_phy>,
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<&pcie1_phy>,
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<&pcie2_phy>,
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<&pcie3_phy>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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};
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tcsr_mutex: hwlock@1905000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0 0x01905000 0 0x20000>;
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1937000 {
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compatible = "qcom,tcsr-ipq5424", "syscon";
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reg = <0 0x01937000 0 0x2a000>;
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};
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qupv3: geniqup@1ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x01ac0000 0 0x2000>;
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ranges;
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clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
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<&gcc GCC_QUPV3_AHB_SLV_CLK>;
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clock-names = "m-ahb", "s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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uart1: serial@1a84000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0 0x01a84000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_UART1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
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};
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spi0: spi@1a90000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x01a90000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@1a94000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x01a94000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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sdhc: mmc@7804000 {
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compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
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reg-names = "hc", "cqhci";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface", "core", "xo";
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supports-cqe;
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status = "disabled";
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};
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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reg = <0 0xf200000 0 0x10000>, /* GICD */
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<0 0xf240000 0 0x80000>; /* GICR * 4 regions */
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#interrupt-cells = <0x3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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mbi-ranges = <672 128>;
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msi-controller;
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};
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watchdog@f410000 {
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compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
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reg = <0 0x0f410000 0 0x1000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sleep_clk>;
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};
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qusb_phy_1: phy@71000 {
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compatible = "qcom,ipq5424-qusb2-phy";
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reg = <0 0x00071000 0 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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<&xo_board>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: usb2@1e00000 {
|
|
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
|
|
reg = <0 0x01ef8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB1_MASTER_CLK>,
|
|
<&gcc GCC_USB1_SLEEP_CLK>,
|
|
<&gcc GCC_USB1_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
|
|
<&gcc GCC_CNOC_USB_CLK>;
|
|
|
|
clock-names = "core",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"iface",
|
|
"cfg_noc";
|
|
|
|
assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
|
|
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
|
|
assigned-clock-rates = <200000000>,
|
|
<24000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"qusb2_phy",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
resets = <&gcc GCC_USB1_BCR>;
|
|
qcom,select-utmi-as-pipe-clk;
|
|
status = "disabled";
|
|
|
|
dwc_1: usb@1e00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x01e00000 0 0xe000>;
|
|
clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&qusb_phy_1>;
|
|
phy-names = "usb2-phy";
|
|
tx-fifo-resize;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
qusb_phy_0: phy@7b000 {
|
|
compatible = "qcom,ipq5424-qusb2-phy";
|
|
reg = <0 0x0007b000 0 0x180>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
|
|
<&xo_board>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssphy_0: phy@7d000 {
|
|
compatible = "qcom,ipq5424-qmp-usb3-phy";
|
|
reg = <0 0x0007d000 0 0xa00>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB0_AUX_CLK>,
|
|
<&xo_board>,
|
|
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
|
|
<&gcc GCC_USB0_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"ref",
|
|
"cfg_ahb",
|
|
"pipe";
|
|
|
|
resets = <&gcc GCC_USB0_PHY_BCR>,
|
|
<&gcc GCC_USB3PHY_0_PHY_BCR>;
|
|
reset-names = "phy",
|
|
"phy_phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb0_pipe_clk";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3: usb3@8a00000 {
|
|
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
|
|
reg = <0 0x08af8800 0 0x400>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_SLEEP_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
|
|
<&gcc GCC_CNOC_USB_CLK>;
|
|
|
|
clock-names = "core",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"iface",
|
|
"cfg_noc";
|
|
|
|
assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
assigned-clock-rates = <200000000>,
|
|
<24000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"qusb2_phy",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
resets = <&gcc GCC_USB_BCR>;
|
|
status = "disabled";
|
|
|
|
dwc_0: usb@8a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x08a00000 0 0xcd00>;
|
|
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&qusb_phy_0>, <&ssphy_0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
tx-fifo-resize;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|
|
};
|
|
|
|
timer@f420000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0 0xf420000 0 0x1000>;
|
|
ranges = <0 0 0 0x10000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
frame@f421000 {
|
|
reg = <0xf421000 0x1000>,
|
|
<0xf422000 0x1000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <0>;
|
|
};
|
|
|
|
frame@f423000 {
|
|
reg = <0xf423000 0x1000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f425000 {
|
|
reg = <0xf425000 0x1000>,
|
|
<0xf426000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f427000 {
|
|
reg = <0xf427000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f429000 {
|
|
reg = <0xf429000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f42b000 {
|
|
reg = <0xf42b000 0x1000>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f42d000 {
|
|
reg = <0xf42d000 0x1000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pcie3: pcie@40000000 {
|
|
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
|
|
reg = <0x0 0x40000000 0x0 0xf1c>,
|
|
<0x0 0x40000f20 0x0 0xa8>,
|
|
<0x0 0x40001000 0x0 0x1000>,
|
|
<0x0 0x000f8000 0x0 0x3000>,
|
|
<0x0 0x40100000 0x0 0x1000>,
|
|
<0x0 0x000fe000 0x0 0x1000>;
|
|
reg-names = "dbi",
|
|
"elbi",
|
|
"atu",
|
|
"parf",
|
|
"config",
|
|
"mhi";
|
|
device_type = "pci";
|
|
linux,pci-domain = <3>;
|
|
num-lanes = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>;
|
|
|
|
msi-map = <0x0 &intc 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE3_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
|
|
<&gcc GCC_PCIE3_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE3_AHB_CLK>,
|
|
<&gcc GCC_PCIE3_AUX_CLK>;
|
|
clock-names = "axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng",
|
|
"ahb",
|
|
"aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE3_PIPE_ARES>,
|
|
<&gcc GCC_PCIE3_CORE_STICKY_RESET>,
|
|
<&gcc GCC_PCIE3_AXI_S_STICKY_RESET>,
|
|
<&gcc GCC_PCIE3_AXI_S_ARES>,
|
|
<&gcc GCC_PCIE3_AXI_M_STICKY_RESET>,
|
|
<&gcc GCC_PCIE3_AXI_M_ARES>,
|
|
<&gcc GCC_PCIE3_AUX_ARES>,
|
|
<&gcc GCC_PCIE3_AHB_ARES>;
|
|
reset-names = "pipe",
|
|
"sticky",
|
|
"axi_s_sticky",
|
|
"axi_s",
|
|
"axi_m_sticky",
|
|
"axi_m",
|
|
"aux",
|
|
"ahb";
|
|
|
|
phys = <&pcie3_phy>;
|
|
phy-names = "pciephy";
|
|
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
|
|
<&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie2: pcie@50000000 {
|
|
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
|
|
reg = <0x0 0x50000000 0x0 0xf1c>,
|
|
<0x0 0x50000f20 0x0 0xa8>,
|
|
<0x0 0x50001000 0x0 0x1000>,
|
|
<0x0 0x000f0000 0x0 0x3000>,
|
|
<0x0 0x50100000 0x0 0x1000>,
|
|
<0x0 0x000f6000 0x0 0x1000>;
|
|
reg-names = "dbi",
|
|
"elbi",
|
|
"atu",
|
|
"parf",
|
|
"config",
|
|
"mhi";
|
|
device_type = "pci";
|
|
linux,pci-domain = <2>;
|
|
num-lanes = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>;
|
|
|
|
msi-map = <0x0 &intc 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE2_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
|
|
<&gcc GCC_PCIE2_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE2_AHB_CLK>,
|
|
<&gcc GCC_PCIE2_AUX_CLK>;
|
|
clock-names = "axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng",
|
|
"ahb",
|
|
"aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE2_PIPE_ARES>,
|
|
<&gcc GCC_PCIE2_CORE_STICKY_RESET>,
|
|
<&gcc GCC_PCIE2_AXI_S_STICKY_RESET>,
|
|
<&gcc GCC_PCIE2_AXI_S_ARES>,
|
|
<&gcc GCC_PCIE2_AXI_M_STICKY_RESET>,
|
|
<&gcc GCC_PCIE2_AXI_M_ARES>,
|
|
<&gcc GCC_PCIE2_AUX_ARES>,
|
|
<&gcc GCC_PCIE2_AHB_ARES>;
|
|
reset-names = "pipe",
|
|
"sticky",
|
|
"axi_s_sticky",
|
|
"axi_s",
|
|
"axi_m_sticky",
|
|
"axi_m",
|
|
"aux",
|
|
"ahb";
|
|
|
|
phys = <&pcie2_phy>;
|
|
phy-names = "pciephy";
|
|
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
|
|
<&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@60000000 {
|
|
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
|
|
reg = <0x0 0x60000000 0x0 0xf1c>,
|
|
<0x0 0x60000f20 0x0 0xa8>,
|
|
<0x0 0x60001000 0x0 0x1000>,
|
|
<0x0 0x00088000 0x0 0x3000>,
|
|
<0x0 0x60100000 0x0 0x1000>,
|
|
<0x0 0x0008e000 0x0 0x1000>;
|
|
reg-names = "dbi",
|
|
"elbi",
|
|
"atu",
|
|
"parf",
|
|
"config",
|
|
"mhi";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>;
|
|
|
|
msi-map = <0x0 &intc 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
|
|
<&gcc GCC_PCIE1_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE1_AHB_CLK>,
|
|
<&gcc GCC_PCIE1_AUX_CLK>;
|
|
clock-names = "axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng",
|
|
"ahb",
|
|
"aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
|
<&gcc GCC_PCIE1_CORE_STICKY_RESET>,
|
|
<&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
|
|
<&gcc GCC_PCIE1_AXI_S_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
|
|
<&gcc GCC_PCIE1_AXI_M_ARES>,
|
|
<&gcc GCC_PCIE1_AUX_ARES>,
|
|
<&gcc GCC_PCIE1_AHB_ARES>;
|
|
reset-names = "pipe",
|
|
"sticky",
|
|
"axi_s_sticky",
|
|
"axi_s",
|
|
"axi_m_sticky",
|
|
"axi_m",
|
|
"aux",
|
|
"ahb";
|
|
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
|
|
<&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie0: pcie@70000000 {
|
|
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
|
|
reg = <0x0 0x70000000 0x0 0xf1c>,
|
|
<0x0 0x70000f20 0x0 0xa8>,
|
|
<0x0 0x70001000 0x0 0x1000>,
|
|
<0x0 0x00080000 0x0 0x3000>,
|
|
<0x0 0x70100000 0x0 0x1000>,
|
|
<0x0 0x00086000 0x0 0x1000>;
|
|
reg-names = "dbi",
|
|
"elbi",
|
|
"atu",
|
|
"parf",
|
|
"config",
|
|
"mhi";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>;
|
|
|
|
msi-map = <0x0 &intc 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
|
|
<&gcc GCC_PCIE0_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE0_AHB_CLK>,
|
|
<&gcc GCC_PCIE0_AUX_CLK>;
|
|
clock-names = "axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng",
|
|
"ahb",
|
|
"aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
|
<&gcc GCC_PCIE0_CORE_STICKY_RESET>,
|
|
<&gcc GCC_PCIE0_AXI_S_STICKY_RESET>,
|
|
<&gcc GCC_PCIE0_AXI_S_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_M_STICKY_RESET>,
|
|
<&gcc GCC_PCIE0_AXI_M_ARES>,
|
|
<&gcc GCC_PCIE0_AUX_ARES>,
|
|
<&gcc GCC_PCIE0_AHB_ARES>;
|
|
reset-names = "pipe",
|
|
"sticky",
|
|
"axi_s_sticky",
|
|
"axi_s",
|
|
"axi_m_sticky",
|
|
"axi_m",
|
|
"aux",
|
|
"ahb";
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
|
|
<&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
cpu0-thermal {
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&tsens 14>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <120000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
|
|
cpu-passive {
|
|
temperature = <110000>;
|
|
hysteresis = <9000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&tsens 12>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <120000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
|
|
cpu-passive {
|
|
temperature = <110000>;
|
|
hysteresis = <9000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-thermal {
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&tsens 11>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <120000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
|
|
cpu-passive {
|
|
temperature = <110000>;
|
|
hysteresis = <9000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-thermal {
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&tsens 13>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <120000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
|
|
cpu-passive {
|
|
temperature = <110000>;
|
|
hysteresis = <9000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-tile2-thermal {
|
|
thermal-sensors = <&tsens 9>;
|
|
|
|
trips {
|
|
wcss-tile2-critical {
|
|
temperature = <125000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-tile3-thermal {
|
|
thermal-sensors = <&tsens 10>;
|
|
|
|
trips {
|
|
wcss-tile3-critical {
|
|
temperature = <125000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
top-glue-thermal {
|
|
thermal-sensors = <&tsens 15>;
|
|
|
|
trips {
|
|
top-glue-critical {
|
|
temperature = <125000>;
|
|
hysteresis = <9000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|