mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
1838d9297f
Enable the PCIe controller and PHY nodes for RDP 441. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250317100029.881286-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
142 lines
2.3 KiB
Plaintext
142 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* IPQ5332 AP-MI01.2 board device tree source
|
|
*
|
|
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "ipq5332-rdp-common.dtsi"
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
|
|
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
|
|
};
|
|
|
|
&blsp1_i2c1 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-0 = <&i2c_1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&sdhc {
|
|
bus-width = <4>;
|
|
max-frequency = <192000000>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
non-removable;
|
|
pinctrl-0 = <&sdc_default_state>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
pinctrl-0 = <&pcie0_default>;
|
|
pinctrl-names = "default";
|
|
|
|
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
|
wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie1 {
|
|
pinctrl-0 = <&pcie1_default>;
|
|
pinctrl-names = "default";
|
|
|
|
perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
|
|
wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie1_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&tlmm {
|
|
i2c_1_pins: i2c-1-state {
|
|
pins = "gpio29", "gpio30";
|
|
function = "blsp1_i2c0";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcie0_default: pcie0-default-state {
|
|
clkreq-n-pins {
|
|
pins = "gpio37";
|
|
function = "pcie0_clk";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
perst-n-pins {
|
|
pins = "gpio38";
|
|
function = "gpio";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
output-low;
|
|
};
|
|
|
|
wake-n-pins {
|
|
pins = "gpio39";
|
|
function = "pcie0_wake";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_default: pcie1-default-state {
|
|
clkreq-n-pins {
|
|
pins = "gpio46";
|
|
function = "pcie1_clk";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
perst-n-pins {
|
|
pins = "gpio47";
|
|
function = "gpio";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
output-low;
|
|
};
|
|
|
|
wake-n-pins {
|
|
pins = "gpio48";
|
|
function = "pcie1_wake";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc_default_state: sdc-default-state {
|
|
clk-pins {
|
|
pins = "gpio13";
|
|
function = "sdc_clk";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio12";
|
|
function = "sdc_cmd";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
function = "sdc_data";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|