mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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43fefd6c71
Enable support for download mode to collect RAM dumps in case of a system crash, allowing post mortem analysis. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250512-ipq5018-syscon-v1-2-eb1ad2414c3c@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
642 lines
15 KiB
Plaintext
642 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* IPQ5018 SoC device tree source
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*
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* Copyright (c) 2023 The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-unified;
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};
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <200000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <200000>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq5018", "qcom,scm";
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qcom,dload-mode = <&tcsr 0x6100>;
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qcom,sdi-enabled;
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};
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};
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memory@40000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x40000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bootloader@4a800000 {
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reg = <0x0 0x4a800000 0x0 0x200000>;
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no-map;
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};
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sbl@4aa00000 {
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reg = <0x0 0x4aa00000 0x0 0x100000>;
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no-map;
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};
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smem@4ab00000 {
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compatible = "qcom,smem";
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reg = <0x0 0x4ab00000 0x0 0x100000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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tz_region: tz@4ac00000 {
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reg = <0x0 0x4ac00000 0x0 0x200000>;
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no-map;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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usbphy0: phy@5b000 {
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compatible = "qcom,ipq5018-usb-hsphy";
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reg = <0x0005b000 0x120>;
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clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
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resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie1_phy: phy@7e000 {
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compatible = "qcom,ipq5018-uniphy-pcie-phy";
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reg = <0x0007e000 0x800>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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num-lanes = <1>;
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status = "disabled";
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};
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pcie0_phy: phy@86000 {
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compatible = "qcom,ipq5018-uniphy-pcie-phy";
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reg = <0x00086000 0x1000>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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num-lanes = <2>;
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 47>;
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interrupt-controller;
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#interrupt-cells = <2>;
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uart1_pins: uart1-state {
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pins = "gpio31", "gpio32", "gpio33", "gpio34";
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function = "blsp1_uart1";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq5018";
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reg = <0x01800000 0x80000>;
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clocks = <&xo_board_clk>,
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<&sleep_clk>,
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsr_mutex: hwlock@1905000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x01905000 0x20000>;
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1937000 {
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compatible = "qcom,tcsr-ipq5018", "syscon";
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reg = <0x01937000 0x21000>;
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};
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000>;
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reg-names = "hc";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board_clk>;
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clock-names = "iface", "core", "xo";
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non-removable;
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status = "disabled";
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};
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x1d000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 4>, <&blsp_dma 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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usb: usb@8af8800 {
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compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
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reg = <0x08af8800 0x400>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq";
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clocks = <&gcc GCC_USB0_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
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<&gcc GCC_USB0_SLEEP_CLK>,
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<&gcc GCC_USB0_MOCK_UTMI_CLK>;
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clock-names = "core",
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"iface",
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"sleep",
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"mock_utmi";
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resets = <&gcc GCC_USB0_BCR>;
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qcom,select-utmi-as-pipe-clk;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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usb_dwc: usb@8a00000 {
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compatible = "snps,dwc3";
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reg = <0x08a00000 0xe000>;
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clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
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clock-names = "ref";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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phy-names = "usb2-phy";
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phys = <&usbphy0>;
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tx-fifo-resize;
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snps,is-utmi-l1-suspend;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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};
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x0b000000 0x1000>, /* GICD */
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<0x0b002000 0x2000>, /* GICC */
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<0x0b001000 0x1000>, /* GICH */
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<0x0b004000 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0b00a000 0x1ffa>;
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v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00000000 0xff8>;
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msi-controller;
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};
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v2m1: v2m@1000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00001000 0xff8>;
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msi-controller;
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};
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};
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watchdog: watchdog@b017000 {
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compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
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reg = <0x0b017000 0x40>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sleep_clk>;
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};
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq5018-apcs-apps-global",
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"qcom,ipq6018-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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#clock-cells = <1>;
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clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
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clock-names = "pll", "xo", "gpll0";
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#mbox-cells = <1>;
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};
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a53pll: clock@b116000 {
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compatible = "qcom,ipq5018-a53pll";
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reg = <0x0b116000 0x40>;
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#clock-cells = <0>;
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clocks = <&xo_board_clk>;
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clock-names = "xo";
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};
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timer@b120000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@b120000 {
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <0>;
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};
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frame@b123000 {
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reg = <0xb123000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <1>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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reg = <0x0b125000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@b126000 {
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reg = <0x0b126000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@b127000 {
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reg = <0x0b127000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@b128000 {
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reg = <0x0b128000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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pcie1: pcie@80000000 {
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compatible = "qcom,pcie-ipq5018";
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reg = <0x80000000 0xf1d>,
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<0x80000f20 0xa8>,
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<0x80001000 0x1000>,
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<0x00078000 0x3000>,
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<0x80100000 0x1000>,
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<0x0007b000 0x1000>;
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reg-names = "dbi",
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"elbi",
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"atu",
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"parf",
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"config",
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"mhi";
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device_type = "pci";
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* The controller supports Gen3, but the connected PHY is Gen2-capable */
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max-link-speed = <2>;
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phys = <&pcie1_phy>;
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phy-names ="pciephy";
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ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
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<0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
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msi-map = <0x0 &v2m0 0x0 0xff8>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
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<&gcc GCC_PCIE1_AXI_M_CLK>,
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<&gcc GCC_PCIE1_AXI_S_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>,
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<&gcc GCC_PCIE1_AUX_CLK>,
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<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
|
|
clock-names = "iface",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"aux",
|
|
"axi_bridge";
|
|
|
|
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
|
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
|
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
|
<&gcc GCC_PCIE1_AHB_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
|
|
reset-names = "pipe",
|
|
"sleep",
|
|
"sticky",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"axi_m_sticky",
|
|
"axi_s_sticky";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie0: pcie@a0000000 {
|
|
compatible = "qcom,pcie-ipq5018";
|
|
reg = <0xa0000000 0xf1d>,
|
|
<0xa0000f20 0xa8>,
|
|
<0xa0001000 0x1000>,
|
|
<0x00080000 0x3000>,
|
|
<0xa0100000 0x1000>,
|
|
<0x00083000 0x1000>;
|
|
reg-names = "dbi",
|
|
"elbi",
|
|
"atu",
|
|
"parf",
|
|
"config",
|
|
"mhi";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
|
|
max-link-speed = <2>;
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names ="pciephy";
|
|
|
|
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
|
|
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
|
|
|
|
msi-map = <0x0 &v2m0 0x0 0xff8>;
|
|
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE0_AHB_CLK>,
|
|
<&gcc GCC_PCIE0_AUX_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
|
|
clock-names = "iface",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"aux",
|
|
"axi_bridge";
|
|
|
|
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
|
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
|
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
|
<&gcc GCC_PCIE0_AHB_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
|
|
reset-names = "pipe",
|
|
"sleep",
|
|
"sticky",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"axi_m_sticky",
|
|
"axi_s_sticky";
|
|
|
|
status = "disabled";
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|