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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 08:32:55 +00:00
a9b906f159
Add in mt8395-genio-1200-evk devicetree file a sub node in pmic for the mt6359-keys compatible to add the Power and Home MT6359 PMIC keys support. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://lore.kernel.org/r/20250703-add-mt6359-pmic-keys-support-v1-3-21a4d2774e34@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
1203 lines
24 KiB
Plaintext
1203 lines
24 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 MediaTek Inc.
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* Author: Ben Lok <ben.lok@mediatek.com>
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* Macpaul Lin <macpaul.lin@mediatek.com>
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*/
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/dts-v1/;
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#include "mt8195.dtsi"
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#include "mt6359.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
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#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/usb/pd.h>
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/ {
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model = "MediaTek Genio 1200 EVK-P1V2-EMMC";
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compatible = "mediatek,mt8395-evk", "mediatek,mt8395",
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"mediatek,mt8195";
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aliases {
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serial0 = &uart0;
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ethernet0 = ð
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0x2 0x00000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* 12 MiB reserved for OP-TEE (BL32)
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* +-----------------------+ 0x43e0_0000
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* | SHMEM 2MiB |
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* +-----------------------+ 0x43c0_0000
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* | | TA_RAM 8MiB |
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* + TZDRAM +--------------+ 0x4340_0000
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* | | TEE_RAM 2MiB |
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* +-----------------------+ 0x4320_0000
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*/
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optee_reserved: optee@43200000 {
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no-map;
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reg = <0 0x43200000 0 0x00c00000>;
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};
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scp_mem: memory@50000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x50000000 0 0x2900000>;
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no-map;
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};
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vpu_mem: memory@53000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
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};
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/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
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bl31_secmon_mem: memory@54600000 {
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no-map;
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reg = <0 0x54600000 0x0 0x200000>;
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};
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adsp_mem: memory@60000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x60000000 0 0xf00000>;
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no-map;
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};
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afe_dma_mem: memory@60f00000 {
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compatible = "shared-dma-pool";
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reg = <0 0x60f00000 0 0x100000>;
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no-map;
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};
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adsp_dma_mem: memory@61000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x61000000 0 0x100000>;
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no-map;
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};
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apu_mem: memory@62000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
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};
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};
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backlight_lcm0: backlight-lcm0 {
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compatible = "pwm-backlight";
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brightness-levels = <0 1023>;
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default-brightness-level = <576>;
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num-interpolated-steps = <1023>;
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pwms = <&disp_pwm0 0 500000>;
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};
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backlight_lcd1: backlight-lcd1 {
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compatible = "pwm-backlight";
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pwms = <&disp_pwm1 0 500000>;
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enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
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brightness-levels = <0 1023>;
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num-interpolated-steps = <1023>;
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default-brightness-level = <576>;
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status = "disabled";
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};
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can_clk: can-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-output-names = "can-clk";
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};
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edp_panel_fixed_3v3: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "edp_panel_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pio 6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&edp_panel_3v3_en_pins>;
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};
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edp_panel_fixed_12v: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "edp_backlight_12v";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&pio 96 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&edp_panel_12v_en_pins>;
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};
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keys: gpio-keys {
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compatible = "gpio-keys";
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button-volume-up {
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wakeup-source;
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debounce-interval = <100>;
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gpios = <&pio 106 GPIO_ACTIVE_LOW>;
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label = "volume_up";
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linux,code = <KEY_VOLUMEUP>;
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};
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};
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lcm0_iovcc: regulator-vio18-lcm0 {
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compatible = "regulator-fixed";
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regulator-name = "vio18_lcm0";
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enable-active-high;
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gpio = <&pio 47 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&dsi0_vreg_en_pins>;
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vin-supply = <&mt6360_ldo2>;
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};
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lcm0_vddp: regulator-vsys-lcm0 {
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compatible = "regulator-fixed";
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regulator-name = "vsys_lcm0";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&mt6360_ldo1>;
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};
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wifi_fixed_3v3: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "wifi_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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};
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&adsp {
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memory-region = <&adsp_dma_mem>, <&adsp_mem>;
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status = "okay";
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};
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&afe {
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memory-region = <&afe_dma_mem>;
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status = "okay";
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};
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&disp_pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&disp_pwm0_pins>;
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status = "okay";
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};
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&dither0_in {
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remote-endpoint = <&gamma0_out>;
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};
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&dither0_out {
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remote-endpoint = <&dsi0_in>;
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};
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&dmic_codec {
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wakeup-delay-ms = <200>;
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};
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&dsi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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panel@0 {
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compatible = "startek,kd070fhfid078", "himax,hx8279";
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reg = <0>;
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backlight = <&backlight_lcm0>;
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enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>;
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iovcc-supply = <&lcm0_iovcc>;
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vdd-supply = <&lcm0_vddp>;
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pinctrl-names = "default";
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pinctrl-0 = <&panel_default_pins>;
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port {
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dsi_panel_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dither0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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remote-endpoint = <&dsi_panel_in>;
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};
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};
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};
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};
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ð {
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phy-mode ="rgmii-rxid";
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phy-handle = <ð_phy0>;
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snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
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snps,reset-delays-us = <0 10000 10000>;
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mediatek,tx-delay-ps = <2030>;
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mediatek,mac-wol;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <ð_default_pins>;
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pinctrl-1 = <ð_sleep_pins>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy0: ethernet-phy@1 {
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compatible = "ethernet-phy-id001c.c916";
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reg = <0x1>;
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};
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};
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};
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&gamma0_out {
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remote-endpoint = <&dither0_in>;
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};
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&gpu {
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mali-supply = <&mt6315_7_vbuck1>;
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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touchscreen@5d {
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compatible = "goodix,gt9271";
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reg = <0x5d>;
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interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>;
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irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
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AVDD28-supply = <&mt6360_ldo1>;
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pinctrl-names = "default";
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pinctrl-0 = <&touch_pins>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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status = "okay";
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typec-mux@48 {
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compatible = "ite,it5205";
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reg = <0x48>;
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vcc-supply = <&mt6359_vibr_ldo_reg>;
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mode-switch;
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orientation-switch;
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status = "okay";
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port {
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it5205_sbu_ep: endpoint {
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remote-endpoint = <&mt6360_ssusb_sbu_ep>;
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};
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};
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};
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};
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&i2c6 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c6_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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mt6360: pmic@34 {
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compatible = "mediatek,mt6360";
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reg = <0x34>;
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interrupt-parent = <&pio>;
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interrupts = <128 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "IRQB";
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interrupt-controller;
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#interrupt-cells = <1>;
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pinctrl-0 = <&mt6360_pins>;
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charger {
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compatible = "mediatek,mt6360-chg";
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richtek,vinovp-microvolt = <14500000>;
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otg_vbus_regulator: usb-otg-vbus-regulator {
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regulator-name = "usb-otg-vbus";
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regulator-min-microvolt = <4425000>;
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regulator-max-microvolt = <5825000>;
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};
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};
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regulator {
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compatible = "mediatek,mt6360-regulator";
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LDO_VIN3-supply = <&mt6360_buck2>;
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mt6360_buck1: buck1 {
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regulator-name = "emi_vdd2";
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1300000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP
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MT6360_OPMODE_ULP>;
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regulator-always-on;
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};
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mt6360_buck2: buck2 {
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regulator-name = "emi_vddq";
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1300000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP
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MT6360_OPMODE_ULP>;
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regulator-always-on;
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};
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mt6360_ldo1: ldo1 {
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regulator-name = "tp1_p3v0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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regulator-always-on;
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};
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mt6360_ldo2: ldo2 {
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regulator-name = "panel1_p1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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};
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mt6360_ldo3: ldo3 {
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regulator-name = "vmc_pmu";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3600000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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};
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mt6360_ldo5: ldo5 {
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regulator-name = "vmch_pmu";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <3600000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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};
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/* This is a measure point, which name is mt6360_ldo1 on schematic */
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mt6360_ldo6: ldo6 {
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regulator-name = "mt6360_ldo1";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <2100000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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};
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mt6360_ldo7: ldo7 {
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regulator-name = "emi_vmddr_en";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <2100000>;
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regulator-allowed-modes = <MT6360_OPMODE_NORMAL
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MT6360_OPMODE_LP>;
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regulator-always-on;
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};
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};
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tcpc {
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compatible = "mediatek,mt6360-tcpc";
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interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "PD_IRQB";
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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op-sink-microwatt = <10000000>;
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power-role = "dual";
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try-power-role = "sink";
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source-pdos = <PDO_FIXED(5000, 1000,
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PDO_FIXED_DUAL_ROLE |
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PDO_FIXED_DATA_SWAP)>;
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sink-pdos = <PDO_FIXED(5000, 2000,
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PDO_FIXED_DUAL_ROLE |
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PDO_FIXED_DATA_SWAP)>;
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pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>;
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altmodes {
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displayport {
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svid = /bits/ 16 <0xff01>;
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vdo = <0x00001c46>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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typec_con_hs: endpoint {
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remote-endpoint = <&mtu3_hs0_role_sw>;
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};
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};
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port@1 {
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reg = <1>;
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typec_con_ss: endpoint {
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remote-endpoint = <&mtu3_ss0_role_sw>;
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};
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};
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port@2 {
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reg = <2>;
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mt6360_ssusb_sbu_ep: endpoint {
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remote-endpoint = <&it5205_sbu_ep>;
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};
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};
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};
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};
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};
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};
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};
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&mfg0 {
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domain-supply = <&mt6315_7_vbuck1>;
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};
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&mfg1 {
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domain-supply = <&mt6359_vsram_others_ldo_reg>;
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};
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&mipi_tx0 {
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status = "okay";
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};
|
|
|
|
&mmc0 {
|
|
status = "okay";
|
|
pinctrl-names = "default", "state_uhs";
|
|
pinctrl-0 = <&mmc0_default_pins>;
|
|
pinctrl-1 = <&mmc0_uhs_pins>;
|
|
bus-width = <8>;
|
|
max-frequency = <200000000>;
|
|
cap-mmc-highspeed;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
cap-mmc-hw-reset;
|
|
no-sdio;
|
|
no-sd;
|
|
hs400-ds-delay = <0x14c11>;
|
|
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
|
|
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
|
|
non-removable;
|
|
};
|
|
|
|
&mmc1 {
|
|
pinctrl-names = "default", "state_uhs";
|
|
pinctrl-0 = <&mmc1_default_pins>;
|
|
pinctrl-1 = <&mmc1_uhs_pins>;
|
|
bus-width = <4>;
|
|
max-frequency = <200000000>;
|
|
cap-sd-highspeed;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
no-mmc;
|
|
no-sdio;
|
|
vmmc-supply = <&mt6360_ldo5>;
|
|
vqmmc-supply = <&mt6360_ldo3>;
|
|
status = "okay";
|
|
non-removable;
|
|
};
|
|
|
|
&mt6359_vaud18_ldo_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6359_vbbck_ldo_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* For USB Hub */
|
|
&mt6359_vcamio_ldo_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6359_vcn33_2_bt_ldo_reg {
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
&mt6359_vcore_buck_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6359_vgpu11_buck_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6359_vpu_buck_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6359_vrf12_ldo_reg {
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* for GPU SRAM */
|
|
&mt6359_vsram_others_ldo_reg {
|
|
regulator-min-microvolt = <750000>;
|
|
regulator-max-microvolt = <750000>;
|
|
};
|
|
|
|
&mt6359codec {
|
|
mediatek,mic-type-0 = <1>; /* ACC */
|
|
mediatek,mic-type-1 = <3>; /* DCC */
|
|
mediatek,mic-type-2 = <1>; /* ACC */
|
|
};
|
|
|
|
&ovl0_in {
|
|
remote-endpoint = <&vdosys0_ep_main>;
|
|
};
|
|
|
|
&pcie0 {
|
|
pinctrl-names = "default", "idle";
|
|
pinctrl-0 = <&pcie0_default_pins>;
|
|
pinctrl-1 = <&pcie0_idle_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie1_default_pins>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&pciephy {
|
|
status = "okay";
|
|
};
|
|
|
|
&pio {
|
|
audio_default_pins: audio-default-pins {
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>,
|
|
<PINMUX_GPIO62__FUNC_DMIC1_DAT>,
|
|
<PINMUX_GPIO65__FUNC_PCM_DO>,
|
|
<PINMUX_GPIO66__FUNC_PCM_CLK>,
|
|
<PINMUX_GPIO67__FUNC_PCM_DI>,
|
|
<PINMUX_GPIO68__FUNC_PCM_SYNC>,
|
|
<PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
|
|
<PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
|
|
<PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
|
|
<PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
|
|
<PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
|
|
<PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
|
|
<PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>;
|
|
};
|
|
};
|
|
|
|
disp_pwm1_default_pins: disp-pwm1-default-pins {
|
|
pins1 {
|
|
pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>;
|
|
};
|
|
};
|
|
|
|
edp_panel_12v_en_pins: edp-panel-12v-en-pins {
|
|
pins1 {
|
|
pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {
|
|
pins1 {
|
|
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
eth_default_pins: eth-default-pins {
|
|
pins-cc {
|
|
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
|
|
<PINMUX_GPIO86__FUNC_GBE_RXC>,
|
|
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
|
|
<PINMUX_GPIO88__FUNC_GBE_TXEN>;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pins-mdio {
|
|
pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
|
|
<PINMUX_GPIO90__FUNC_GBE_MDIO>;
|
|
input-enable;
|
|
};
|
|
|
|
pins-power {
|
|
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
|
|
<PINMUX_GPIO92__FUNC_GPIO92>;
|
|
output-high;
|
|
};
|
|
|
|
pins-rxd {
|
|
pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
|
|
<PINMUX_GPIO82__FUNC_GBE_RXD2>,
|
|
<PINMUX_GPIO83__FUNC_GBE_RXD1>,
|
|
<PINMUX_GPIO84__FUNC_GBE_RXD0>;
|
|
};
|
|
|
|
pins-txd {
|
|
pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
|
|
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
|
|
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
|
|
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
|
|
drive-strength = <8>;
|
|
};
|
|
};
|
|
|
|
eth_sleep_pins: eth-sleep-pins {
|
|
pins-cc {
|
|
pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
|
|
<PINMUX_GPIO86__FUNC_GPIO86>,
|
|
<PINMUX_GPIO87__FUNC_GPIO87>,
|
|
<PINMUX_GPIO88__FUNC_GPIO88>;
|
|
};
|
|
|
|
pins-mdio {
|
|
pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
|
|
<PINMUX_GPIO90__FUNC_GPIO90>;
|
|
input-disable;
|
|
bias-disable;
|
|
};
|
|
|
|
pins-rxd {
|
|
pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
|
|
<PINMUX_GPIO82__FUNC_GPIO82>,
|
|
<PINMUX_GPIO83__FUNC_GPIO83>,
|
|
<PINMUX_GPIO84__FUNC_GPIO84>;
|
|
};
|
|
|
|
pins-txd {
|
|
pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
|
|
<PINMUX_GPIO78__FUNC_GPIO78>,
|
|
<PINMUX_GPIO79__FUNC_GPIO79>,
|
|
<PINMUX_GPIO80__FUNC_GPIO80>;
|
|
};
|
|
};
|
|
|
|
gpio_key_pins: gpio-keys-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
|
|
bias-pull-up;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2c0_pins: i2c0-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
|
|
<PINMUX_GPIO9__FUNC_SCL0>;
|
|
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
|
|
drive-strength-microamp = <1000>;
|
|
};
|
|
};
|
|
|
|
i2c1_pins: i2c1-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
|
|
<PINMUX_GPIO11__FUNC_SCL1>;
|
|
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
|
|
drive-strength-microamp = <1000>;
|
|
};
|
|
};
|
|
|
|
i2c2_pins: i2c2-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
|
|
<PINMUX_GPIO13__FUNC_SCL2>;
|
|
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
|
|
drive-strength = <6>;
|
|
};
|
|
};
|
|
|
|
i2c6_pins: i2c6-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
|
|
<PINMUX_GPIO26__FUNC_SCL6>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
mmc0_default_pins: mmc0-default-pins {
|
|
pins-clk {
|
|
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
|
|
drive-strength = <6>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
};
|
|
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
|
|
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
|
|
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
|
|
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
|
|
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
|
|
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
|
|
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
|
|
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
|
|
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
|
|
input-enable;
|
|
drive-strength = <6>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
|
|
pins-rst {
|
|
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
|
|
drive-strength = <6>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
};
|
|
|
|
mmc0_uhs_pins: mmc0-uhs-pins {
|
|
pins-clk {
|
|
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
|
|
drive-strength = <8>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
};
|
|
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
|
|
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
|
|
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
|
|
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
|
|
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
|
|
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
|
|
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
|
|
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
|
|
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
|
|
input-enable;
|
|
drive-strength = <8>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
|
|
pins-ds {
|
|
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
|
|
drive-strength = <8>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
};
|
|
|
|
pins-rst {
|
|
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
|
|
drive-strength = <8>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
};
|
|
|
|
mmc1_default_pins: mmc1-default-pins {
|
|
pins-clk {
|
|
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
|
|
drive-strength = <8>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
};
|
|
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
|
|
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
|
|
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
|
|
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
|
|
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
|
|
input-enable;
|
|
drive-strength = <8>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
};
|
|
|
|
mmc1_uhs_pins: mmc1-uhs-pins {
|
|
pins-clk {
|
|
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
|
|
drive-strength = <8>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
};
|
|
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
|
|
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
|
|
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
|
|
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
|
|
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
|
|
input-enable;
|
|
drive-strength = <8>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
};
|
|
};
|
|
|
|
mt6360_pins: mt6360-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>,
|
|
<PINMUX_GPIO128__FUNC_GPIO128>;
|
|
input-enable;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
dsi0_vreg_en_pins: dsi0-vreg-en-pins {
|
|
pins-pwr-en {
|
|
pinmux = <PINMUX_GPIO47__FUNC_GPIO47>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
panel_default_pins: panel-default-pins {
|
|
pins-rst {
|
|
pinmux = <PINMUX_GPIO108__FUNC_GPIO108>;
|
|
output-high;
|
|
};
|
|
|
|
pins-en {
|
|
pinmux = <PINMUX_GPIO48__FUNC_GPIO48>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
pcie0_default_pins: pcie0-default-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
|
|
<PINMUX_GPIO20__FUNC_PERSTN>,
|
|
<PINMUX_GPIO21__FUNC_CLKREQN>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_idle_pins: pcie0-idle-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
pcie1_default_pins: pcie1-default-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
|
|
<PINMUX_GPIO23__FUNC_CLKREQN_1>,
|
|
<PINMUX_GPIO24__FUNC_WAKEN_1>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
disp_pwm0_pins: disp-pwm0-pins {
|
|
pins-disp-pwm {
|
|
pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
|
|
};
|
|
};
|
|
|
|
spi1_pins: spi1-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
|
|
<PINMUX_GPIO137__FUNC_SPIM1_CLK>,
|
|
<PINMUX_GPIO138__FUNC_SPIM1_MO>,
|
|
<PINMUX_GPIO139__FUNC_SPIM1_MI>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
spi2_pins: spi-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
|
|
<PINMUX_GPIO141__FUNC_SPIM2_CLK>,
|
|
<PINMUX_GPIO142__FUNC_SPIM2_MO>,
|
|
<PINMUX_GPIO143__FUNC_SPIM2_MI>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
touch_pins: touch-pins {
|
|
pins-irq {
|
|
pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
|
|
pins-reset {
|
|
pinmux = <PINMUX_GPIO133__FUNC_GPIO133>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
u3_p0_vbus: u3-p0-vbus-default-pins {
|
|
pins-vbus {
|
|
pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
uart0_pins: uart0-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
|
|
<PINMUX_GPIO99__FUNC_URXD0>;
|
|
};
|
|
};
|
|
|
|
uart1_pins: uart1-pins {
|
|
pins {
|
|
pinmux = <PINMUX_GPIO100__FUNC_URTS1>,
|
|
<PINMUX_GPIO101__FUNC_UCTS1>,
|
|
<PINMUX_GPIO102__FUNC_UTXD1>,
|
|
<PINMUX_GPIO103__FUNC_URXD1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pmic {
|
|
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
mt6359keys: keys {
|
|
compatible = "mediatek,mt6359-keys";
|
|
mediatek,long-press-mode = <1>;
|
|
power-off-time-sec = <0>;
|
|
|
|
power-key {
|
|
linux,keycodes = <KEY_POWER>;
|
|
wakeup-source;
|
|
};
|
|
|
|
home {
|
|
linux,keycodes = <KEY_HOME>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&scp {
|
|
memory-region = <&scp_mem>;
|
|
firmware-name = "mediatek/mt8195/scp.img";
|
|
status = "okay";
|
|
};
|
|
|
|
&sound {
|
|
compatible = "mediatek,mt8195_mt6359";
|
|
model = "mt8395-evk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&audio_default_pins>;
|
|
audio-routing =
|
|
"Headphone", "Headphone L",
|
|
"Headphone", "Headphone R";
|
|
mediatek,adsp = <&adsp>;
|
|
status = "okay";
|
|
|
|
headphone-dai-link {
|
|
link-name = "DL_SRC_BE";
|
|
|
|
codec {
|
|
sound-dai = <&pmic 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi1 {
|
|
pinctrl-0 = <&spi1_pins>;
|
|
pinctrl-names = "default";
|
|
mediatek,pad-select = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>;
|
|
|
|
can0: can@0 {
|
|
compatible = "microchip,mcp2518fd";
|
|
reg = <0>;
|
|
clocks = <&can_clk>;
|
|
spi-max-frequency = <20000000>;
|
|
interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>;
|
|
vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
|
|
xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
|
|
};
|
|
};
|
|
|
|
&spi2 {
|
|
pinctrl-0 = <&spi2_pins>;
|
|
pinctrl-names = "default";
|
|
mediatek,pad-select = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&spmi {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
mt6315_6: pmic@6 {
|
|
compatible = "mediatek,mt6315-regulator";
|
|
reg = <0x6 SPMI_USID>;
|
|
|
|
regulators {
|
|
mt6315_6_vbuck1: vbuck1 {
|
|
regulator-name = "Vbcpu";
|
|
regulator-min-microvolt = <300000>;
|
|
regulator-max-microvolt = <1193750>;
|
|
regulator-enable-ramp-delay = <256>;
|
|
regulator-allowed-modes = <0 1 2>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
mt6315_7: pmic@7 {
|
|
compatible = "mediatek,mt6315-regulator";
|
|
reg = <0x7 SPMI_USID>;
|
|
|
|
regulators {
|
|
mt6315_7_vbuck1: vbuck1 {
|
|
regulator-name = "Vgpu";
|
|
regulator-min-microvolt = <546000>;
|
|
regulator-max-microvolt = <787000>;
|
|
regulator-enable-ramp-delay = <256>;
|
|
regulator-allowed-modes = <0 1 2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&u3phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u3phy1 {
|
|
status = "okay";
|
|
|
|
u3port1: usb-phy@700 {
|
|
mediatek,force-mode;
|
|
};
|
|
};
|
|
|
|
&u3phy2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u3phy3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
pinctrl-0 = <&uart0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-0 = <&uart1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&ufsphy {
|
|
status = "disabled";
|
|
};
|
|
|
|
&ssusb0 {
|
|
dr_mode = "otg";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&u3_p0_vbus>;
|
|
usb-role-switch;
|
|
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
mtu3_hs0_role_sw: endpoint {
|
|
remote-endpoint = <&typec_con_hs>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
mtu3_ss0_role_sw: endpoint {
|
|
remote-endpoint = <&typec_con_ss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&ssusb2 {
|
|
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
|
status = "okay";
|
|
};
|
|
|
|
&ssusb3 {
|
|
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
|
status = "okay";
|
|
};
|
|
|
|
&vdosys0 {
|
|
port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vdosys0_ep_main: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&ovl0_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&xhci0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xhci1 {
|
|
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
|
status = "okay";
|
|
};
|
|
|
|
&xhci2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xhci3 {
|
|
status = "okay";
|
|
};
|