mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 08:32:55 +00:00
253b4e96f5
The current DT has the wakeup-source and mediatek,syscon-wakeup
properties in the XHCI nodes, which configures USB wakeup after powering
down the XHCI hardware block. However, since the XHCI controller is
behind an MTU3 (USB3 DRD controller), the MTU3 only gets powered down
after USB wakeup has been configured, causing the system to detect a
wakeup, and results in broken suspend support as the system resumes
immediately.
Move the wakeup properties to the MTU3 nodes so that USB wakeup is only
enabled after the MTU3 has powered down.
With this change in place, it is possible to suspend and resume, and
also to wakeup through USB, as tested on the Google Steelix (Lenovo 300e
Yoga Chromebook Gen 4).
Fixes: f6c3e61c54 ("arm64: dts: mediatek: mt8186: Add MTU3 nodes")
Reported-by: Wojciech Macek <wmacek@google.com>
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241106-mt8186-suspend-with-usb-wakeup-v1-1-07734a4c8236@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2522 lines
67 KiB
Plaintext
2522 lines
67 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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*/
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/dts-v1/;
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#include <dt-bindings/clock/mt8186-clk.h>
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#include <dt-bindings/gce/mt8186-gce.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/mt8186-memory-port.h>
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#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
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#include <dt-bindings/power/mt8186-power.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt8186-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
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/ {
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compatible = "mediatek,mt8186";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ovl0 = &ovl0;
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ovl-2l0 = &ovl_2l0;
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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};
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fhctl: fhctl@1000ce00 {
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compatible = "mediatek,mt8186-fhctl";
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clocks = <&apmixedsys CLK_APMIXED_TVDPLL>;
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reg = <0 0x1000ce00 0 0x200>;
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status = "disabled";
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};
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cci: cci {
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compatible = "mediatek,mt8186-cci";
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clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cci", "intermediate";
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operating-points-v2 = <&cci_opp>;
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};
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cci_opp: opp-table-cci {
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compatible = "operating-points-v2";
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opp-shared;
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cci_opp_0: opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <600000>;
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};
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cci_opp_1: opp-560000000 {
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opp-hz = /bits/ 64 <560000000>;
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opp-microvolt = <675000>;
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};
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cci_opp_2: opp-612000000 {
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opp-hz = /bits/ 64 <612000000>;
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opp-microvolt = <693750>;
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};
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cci_opp_3: opp-682000000 {
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opp-hz = /bits/ 64 <682000000>;
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opp-microvolt = <718750>;
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};
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cci_opp_4: opp-752000000 {
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opp-hz = /bits/ 64 <752000000>;
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opp-microvolt = <743750>;
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};
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cci_opp_5: opp-822000000 {
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opp-hz = /bits/ 64 <822000000>;
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opp-microvolt = <768750>;
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};
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cci_opp_6: opp-875000000 {
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opp-hz = /bits/ 64 <875000000>;
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opp-microvolt = <781250>;
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};
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cci_opp_7: opp-927000000 {
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opp-hz = /bits/ 64 <927000000>;
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opp-microvolt = <800000>;
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};
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cci_opp_8: opp-980000000 {
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opp-hz = /bits/ 64 <980000000>;
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opp-microvolt = <818750>;
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};
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cci_opp_9: opp-1050000000 {
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opp-hz = /bits/ 64 <1050000000>;
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opp-microvolt = <843750>;
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};
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cci_opp_10: opp-1120000000 {
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opp-hz = /bits/ 64 <1120000000>;
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opp-microvolt = <862500>;
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};
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cci_opp_11: opp-1155000000 {
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opp-hz = /bits/ 64 <1155000000>;
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opp-microvolt = <887500>;
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};
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cci_opp_12: opp-1190000000 {
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opp-hz = /bits/ 64 <1190000000>;
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opp-microvolt = <906250>;
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};
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cci_opp_13: opp-1260000000 {
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opp-hz = /bits/ 64 <1260000000>;
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opp-microvolt = <950000>;
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};
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cci_opp_14: opp-1330000000 {
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opp-hz = /bits/ 64 <1330000000>;
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opp-microvolt = <993750>;
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};
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cci_opp_15: opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <1031250>;
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};
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};
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cluster0_opp: opp-table-cluster0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <600000>;
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required-opps = <&cci_opp_0>;
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};
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opp-774000000 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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required-opps = <&cci_opp_1>;
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};
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opp-875000000 {
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opp-hz = /bits/ 64 <875000000>;
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opp-microvolt = <700000>;
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required-opps = <&cci_opp_2>;
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};
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opp-975000000 {
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opp-hz = /bits/ 64 <975000000>;
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opp-microvolt = <725000>;
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required-opps = <&cci_opp_3>;
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};
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opp-1075000000 {
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opp-hz = /bits/ 64 <1075000000>;
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opp-microvolt = <750000>;
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required-opps = <&cci_opp_4>;
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};
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opp-1175000000 {
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opp-hz = /bits/ 64 <1175000000>;
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opp-microvolt = <775000>;
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required-opps = <&cci_opp_5>;
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};
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opp-1275000000 {
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opp-hz = /bits/ 64 <1275000000>;
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opp-microvolt = <800000>;
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required-opps = <&cci_opp_6>;
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};
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opp-1375000000 {
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opp-hz = /bits/ 64 <1375000000>;
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opp-microvolt = <825000>;
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required-opps = <&cci_opp_7>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <856250>;
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required-opps = <&cci_opp_8>;
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};
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opp-1618000000 {
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opp-hz = /bits/ 64 <1618000000>;
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opp-microvolt = <875000>;
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required-opps = <&cci_opp_9>;
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};
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opp-1666000000 {
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opp-hz = /bits/ 64 <1666000000>;
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opp-microvolt = <900000>;
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required-opps = <&cci_opp_10>;
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};
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opp-1733000000 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <925000>;
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required-opps = <&cci_opp_11>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <950000>;
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required-opps = <&cci_opp_12>;
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};
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opp-1866000000 {
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opp-hz = /bits/ 64 <1866000000>;
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opp-microvolt = <981250>;
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required-opps = <&cci_opp_13>;
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};
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opp-1933000000 {
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opp-hz = /bits/ 64 <1933000000>;
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opp-microvolt = <1006250>;
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required-opps = <&cci_opp_14>;
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};
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opp-2000000000 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <1031250>;
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required-opps = <&cci_opp_15>;
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};
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};
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cluster1_opp: opp-table-cluster1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-774000000 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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required-opps = <&cci_opp_0>;
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};
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opp-835000000 {
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opp-hz = /bits/ 64 <835000000>;
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opp-microvolt = <693750>;
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required-opps = <&cci_opp_1>;
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};
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opp-919000000 {
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opp-hz = /bits/ 64 <919000000>;
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opp-microvolt = <718750>;
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required-opps = <&cci_opp_2>;
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};
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opp-1002000000 {
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opp-hz = /bits/ 64 <1002000000>;
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opp-microvolt = <743750>;
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required-opps = <&cci_opp_3>;
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};
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opp-1085000000 {
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opp-hz = /bits/ 64 <1085000000>;
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opp-microvolt = <775000>;
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required-opps = <&cci_opp_4>;
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};
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opp-1169000000 {
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opp-hz = /bits/ 64 <1169000000>;
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opp-microvolt = <800000>;
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required-opps = <&cci_opp_5>;
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};
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opp-1308000000 {
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opp-hz = /bits/ 64 <1308000000>;
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opp-microvolt = <843750>;
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required-opps = <&cci_opp_6>;
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};
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opp-1419000000 {
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opp-hz = /bits/ 64 <1419000000>;
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opp-microvolt = <875000>;
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required-opps = <&cci_opp_7>;
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};
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opp-1530000000 {
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opp-hz = /bits/ 64 <1530000000>;
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opp-microvolt = <912500>;
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required-opps = <&cci_opp_8>;
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};
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opp-1670000000 {
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opp-hz = /bits/ 64 <1670000000>;
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opp-microvolt = <956250>;
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required-opps = <&cci_opp_9>;
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};
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opp-1733000000 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <981250>;
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required-opps = <&cci_opp_10>;
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};
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opp-1796000000 {
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opp-hz = /bits/ 64 <1796000000>;
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opp-microvolt = <1012500>;
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required-opps = <&cci_opp_11>;
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};
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opp-1860000000 {
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opp-hz = /bits/ 64 <1860000000>;
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opp-microvolt = <1037500>;
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required-opps = <&cci_opp_12>;
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};
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opp-1923000000 {
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opp-hz = /bits/ 64 <1923000000>;
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opp-microvolt = <1062500>;
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required-opps = <&cci_opp_13>;
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};
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cluster1_opp_14: opp-1986000000 {
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opp-hz = /bits/ 64 <1986000000>;
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opp-microvolt = <1093750>;
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required-opps = <&cci_opp_14>;
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};
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cluster1_opp_15: opp-2050000000 {
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opp-hz = /bits/ 64 <2050000000>;
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opp-microvolt = <1118750>;
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required-opps = <&cci_opp_15>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x000>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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mediatek,cci = <&cci>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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mediatek,cci = <&cci>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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mediatek,cci = <&cci>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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mediatek,cci = <&cci>;
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x400>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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mediatek,cci = <&cci>;
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};
|
|
|
|
cpu5: cpu@500 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x500>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2000000000>;
|
|
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
dynamic-power-coefficient = <84>;
|
|
capacity-dmips-mhz = <382>;
|
|
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
|
i-cache-size = <32768>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <128>;
|
|
d-cache-size = <32768>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&l2_0>;
|
|
#cooling-cells = <2>;
|
|
mediatek,cci = <&cci>;
|
|
};
|
|
|
|
cpu6: cpu@600 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0x600>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2050000000>;
|
|
clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <335>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
|
|
i-cache-size = <65536>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <65536>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <256>;
|
|
next-level-cache = <&l2_1>;
|
|
#cooling-cells = <2>;
|
|
mediatek,cci = <&cci>;
|
|
};
|
|
|
|
cpu7: cpu@700 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0x700>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2050000000>;
|
|
clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <335>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
|
|
i-cache-size = <65536>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <65536>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <256>;
|
|
next-level-cache = <&l2_1>;
|
|
#cooling-cells = <2>;
|
|
mediatek,cci = <&cci>;
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
cpu_ret_l: cpu-retention-l {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x00010001>;
|
|
local-timer-stop;
|
|
entry-latency-us = <50>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <1600>;
|
|
};
|
|
|
|
cpu_ret_b: cpu-retention-b {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x00010001>;
|
|
local-timer-stop;
|
|
entry-latency-us = <50>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <1400>;
|
|
};
|
|
|
|
cpu_off_l: cpu-off-l {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010001>;
|
|
local-timer-stop;
|
|
entry-latency-us = <100>;
|
|
exit-latency-us = <250>;
|
|
min-residency-us = <2100>;
|
|
};
|
|
|
|
cpu_off_b: cpu-off-b {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010001>;
|
|
local-timer-stop;
|
|
entry-latency-us = <100>;
|
|
exit-latency-us = <250>;
|
|
min-residency-us = <1900>;
|
|
};
|
|
};
|
|
|
|
l2_0: l2-cache0 {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-size = <131072>;
|
|
cache-line-size = <64>;
|
|
cache-sets = <512>;
|
|
next-level-cache = <&l3_0>;
|
|
cache-unified;
|
|
};
|
|
|
|
l2_1: l2-cache1 {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-size = <262144>;
|
|
cache-line-size = <64>;
|
|
cache-sets = <512>;
|
|
next-level-cache = <&l3_0>;
|
|
cache-unified;
|
|
};
|
|
|
|
l3_0: l3-cache {
|
|
compatible = "cache";
|
|
cache-level = <3>;
|
|
cache-size = <1048576>;
|
|
cache-line-size = <64>;
|
|
cache-sets = <1024>;
|
|
cache-unified;
|
|
};
|
|
};
|
|
|
|
clk13m: fixed-factor-clock-13m {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clocks = <&clk26m>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "clk13m";
|
|
};
|
|
|
|
clk26m: oscillator-26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
clock-output-names = "clk26m";
|
|
};
|
|
|
|
clk32k: oscillator-32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "clk32k";
|
|
};
|
|
|
|
gpu_opp_table: opp-table-gpu {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-299000000 {
|
|
opp-hz = /bits/ 64 <299000000>;
|
|
opp-microvolt = <612500>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-332000000 {
|
|
opp-hz = /bits/ 64 <332000000>;
|
|
opp-microvolt = <625000>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-366000000 {
|
|
opp-hz = /bits/ 64 <366000000>;
|
|
opp-microvolt = <637500>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-400000000 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
opp-microvolt = <643750>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-434000000 {
|
|
opp-hz = /bits/ 64 <434000000>;
|
|
opp-microvolt = <656250>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-484000000 {
|
|
opp-hz = /bits/ 64 <484000000>;
|
|
opp-microvolt = <668750>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-535000000 {
|
|
opp-hz = /bits/ 64 <535000000>;
|
|
opp-microvolt = <687500>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-586000000 {
|
|
opp-hz = /bits/ 64 <586000000>;
|
|
opp-microvolt = <700000>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-637000000 {
|
|
opp-hz = /bits/ 64 <637000000>;
|
|
opp-microvolt = <712500>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-690000000 {
|
|
opp-hz = /bits/ 64 <690000000>;
|
|
opp-microvolt = <737500>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-743000000 {
|
|
opp-hz = /bits/ 64 <743000000>;
|
|
opp-microvolt = <756250>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-796000000 {
|
|
opp-hz = /bits/ 64 <796000000>;
|
|
opp-microvolt = <781250>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-850000000 {
|
|
opp-hz = /bits/ 64 <850000000>;
|
|
opp-microvolt = <800000>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-900000000-3 {
|
|
opp-hz = /bits/ 64 <900000000>;
|
|
opp-microvolt = <850000>;
|
|
opp-supported-hw = <0xcf>;
|
|
};
|
|
|
|
opp-900000000-4 {
|
|
opp-hz = /bits/ 64 <900000000>;
|
|
opp-microvolt = <837500>;
|
|
opp-supported-hw = <0x10>;
|
|
};
|
|
|
|
opp-900000000-5 {
|
|
opp-hz = /bits/ 64 <900000000>;
|
|
opp-microvolt = <825000>;
|
|
opp-supported-hw = <0x20>;
|
|
};
|
|
|
|
opp-950000000-3 {
|
|
opp-hz = /bits/ 64 <950000000>;
|
|
opp-microvolt = <900000>;
|
|
opp-supported-hw = <0xcf>;
|
|
};
|
|
|
|
opp-950000000-4 {
|
|
opp-hz = /bits/ 64 <950000000>;
|
|
opp-microvolt = <875000>;
|
|
opp-supported-hw = <0x10>;
|
|
};
|
|
|
|
opp-950000000-5 {
|
|
opp-hz = /bits/ 64 <950000000>;
|
|
opp-microvolt = <850000>;
|
|
opp-supported-hw = <0x20>;
|
|
};
|
|
|
|
opp-1000000000-3 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <950000>;
|
|
opp-supported-hw = <0xcf>;
|
|
};
|
|
|
|
opp-1000000000-4 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <912500>;
|
|
opp-supported-hw = <0x10>;
|
|
};
|
|
|
|
opp-1000000000-5 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <875000>;
|
|
opp-supported-hw = <0x20>;
|
|
};
|
|
};
|
|
|
|
pmu-a55 {
|
|
compatible = "arm,cortex-a55-pmu";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
|
|
};
|
|
|
|
pmu-a76 {
|
|
compatible = "arm,cortex-a76-pmu";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
ranges;
|
|
|
|
gic: interrupt-controller@c000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <4>;
|
|
#redistributor-regions = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0 0x0c000000 0 0x40000>,
|
|
<0 0x0c040000 0 0x200000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
ppi-partitions {
|
|
ppi_cluster0: interrupt-partition-0 {
|
|
affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
|
|
};
|
|
|
|
ppi_cluster1: interrupt-partition-1 {
|
|
affinity = <&cpu6 &cpu7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mcusys: syscon@c53a000 {
|
|
compatible = "mediatek,mt8186-mcusys", "syscon";
|
|
reg = <0 0xc53a000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
topckgen: syscon@10000000 {
|
|
compatible = "mediatek,mt8186-topckgen", "syscon";
|
|
reg = <0 0x10000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg_ao: syscon@10001000 {
|
|
compatible = "mediatek,mt8186-infracfg_ao", "syscon";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pericfg: syscon@10003000 {
|
|
compatible = "mediatek,mt8186-pericfg", "syscon";
|
|
reg = <0 0x10003000 0 0x1000>;
|
|
};
|
|
|
|
pio: pinctrl@10005000 {
|
|
compatible = "mediatek,mt8186-pinctrl";
|
|
reg = <0 0x10005000 0 0x1000>,
|
|
<0 0x10002000 0 0x0200>,
|
|
<0 0x10002200 0 0x0200>,
|
|
<0 0x10002400 0 0x0200>,
|
|
<0 0x10002600 0 0x0200>,
|
|
<0 0x10002a00 0 0x0200>,
|
|
<0 0x10002c00 0 0x0200>,
|
|
<0 0x1000b000 0 0x1000>;
|
|
reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
|
|
"iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pio 0 0 185>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
scpsys: syscon@10006000 {
|
|
compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
|
|
/* System Power Manager */
|
|
spm: power-controller {
|
|
compatible = "mediatek,mt8186-power-controller";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
/* power domain of the SoC */
|
|
mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
|
|
reg = <MT8186_POWER_DOMAIN_MFG0>;
|
|
clocks = <&topckgen CLK_TOP_MFG>;
|
|
clock-names = "mfg00";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
|
|
reg = <MT8186_POWER_DOMAIN_MFG1>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_MFG2 {
|
|
reg = <MT8186_POWER_DOMAIN_MFG2>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_MFG3 {
|
|
reg = <MT8186_POWER_DOMAIN_MFG3>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
|
|
reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
|
|
clocks = <&topckgen CLK_TOP_SENINF>,
|
|
<&topckgen CLK_TOP_SENINF1>;
|
|
clock-names = "subsys-csirx-top0",
|
|
"subsys-csirx-top1";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_SSUSB {
|
|
reg = <MT8186_POWER_DOMAIN_SSUSB>;
|
|
clocks = <&topckgen CLK_TOP_USB_TOP>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
|
|
reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
|
|
reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
|
|
clocks = <&topckgen CLK_TOP_AUDIODSP>,
|
|
<&topckgen CLK_TOP_ADSP_BUS>;
|
|
clock-names = "audioadsp",
|
|
"subsys-adsp-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
|
|
reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
|
|
reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_CONN_ON {
|
|
reg = <MT8186_POWER_DOMAIN_CONN_ON>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_DIS {
|
|
reg = <MT8186_POWER_DOMAIN_DIS>;
|
|
clocks = <&topckgen CLK_TOP_DISP>,
|
|
<&topckgen CLK_TOP_MDP>,
|
|
<&mmsys CLK_MM_SMI_INFRA>,
|
|
<&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_GALS>,
|
|
<&mmsys CLK_MM_SMI_IOMMU>;
|
|
clock-names = "disp", "mdp",
|
|
"subsys-smi-infra",
|
|
"subsys-smi-common",
|
|
"subsys-smi-gals",
|
|
"subsys-smi-iommu";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_VDEC {
|
|
reg = <MT8186_POWER_DOMAIN_VDEC>;
|
|
clocks = <&topckgen CLK_TOP_VDEC>,
|
|
<&vdecsys CLK_VDEC_LARB1_CKEN>;
|
|
clock-names = "vdec0", "larb";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_CAM {
|
|
reg = <MT8186_POWER_DOMAIN_CAM>;
|
|
clocks = <&topckgen CLK_TOP_SENINF>,
|
|
<&topckgen CLK_TOP_SENINF1>,
|
|
<&topckgen CLK_TOP_SENINF2>,
|
|
<&topckgen CLK_TOP_SENINF3>,
|
|
<&camsys CLK_CAM2MM_GALS>,
|
|
<&topckgen CLK_TOP_CAMTM>,
|
|
<&topckgen CLK_TOP_CAM>;
|
|
clock-names = "cam0", "cam1", "cam2",
|
|
"cam3", "gals",
|
|
"subsys-cam-tm",
|
|
"subsys-cam-top";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
|
|
reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
|
|
reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_IMG {
|
|
reg = <MT8186_POWER_DOMAIN_IMG>;
|
|
clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
|
|
<&topckgen CLK_TOP_IMG1>;
|
|
clock-names = "gals", "subsys-img-top";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_IMG2 {
|
|
reg = <MT8186_POWER_DOMAIN_IMG2>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_IPE {
|
|
reg = <MT8186_POWER_DOMAIN_IPE>;
|
|
clocks = <&topckgen CLK_TOP_IPE>,
|
|
<&ipesys CLK_IPE_LARB19>,
|
|
<&ipesys CLK_IPE_LARB20>,
|
|
<&ipesys CLK_IPE_SMI_SUBCOM>,
|
|
<&ipesys CLK_IPE_GALS_IPE>;
|
|
clock-names = "subsys-ipe-top",
|
|
"subsys-ipe-larb0",
|
|
"subsys-ipe-larb1",
|
|
"subsys-ipe-smi",
|
|
"subsys-ipe-gals";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_VENC {
|
|
reg = <MT8186_POWER_DOMAIN_VENC>;
|
|
clocks = <&topckgen CLK_TOP_VENC>,
|
|
<&vencsys CLK_VENC_CKE1_VENC>;
|
|
clock-names = "venc0", "subsys-larb";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
power-domain@MT8186_POWER_DOMAIN_WPE {
|
|
reg = <MT8186_POWER_DOMAIN_WPE>;
|
|
clocks = <&topckgen CLK_TOP_WPE>,
|
|
<&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
|
|
<&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
|
|
clock-names = "wpe0",
|
|
"subsys-larb-ck",
|
|
"subsys-larb-pclk";
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
watchdog: watchdog@10007000 {
|
|
compatible = "mediatek,mt8186-wdt";
|
|
mediatek,disable-extrst;
|
|
reg = <0 0x10007000 0 0x1000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apmixedsys: syscon@1000c000 {
|
|
compatible = "mediatek,mt8186-apmixedsys", "syscon";
|
|
reg = <0 0x1000c000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pwrap: pwrap@1000d000 {
|
|
compatible = "mediatek,mt8186-pwrap", "syscon";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
reg-names = "pwrap";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
|
|
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
|
|
clock-names = "spi", "wrap";
|
|
};
|
|
|
|
spmi: spmi@10015000 {
|
|
compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
|
|
reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
|
|
reg-names = "pmif", "spmimst";
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
|
|
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
|
|
<&topckgen CLK_TOP_SPMI_MST>;
|
|
clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
|
|
assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
|
|
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
systimer: timer@10017000 {
|
|
compatible = "mediatek,mt8186-timer",
|
|
"mediatek,mt6765-timer";
|
|
reg = <0 0x10017000 0 0x1000>;
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk13m>;
|
|
};
|
|
|
|
gce: mailbox@1022c000 {
|
|
compatible = "mediatek,mt8186-gce";
|
|
reg = <0 0X1022c000 0 0x4000>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
|
|
clock-names = "gce";
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
scp: scp@10500000 {
|
|
compatible = "mediatek,mt8186-scp";
|
|
reg = <0 0x10500000 0 0x40000>,
|
|
<0 0x105c0000 0 0x19080>;
|
|
reg-names = "sram", "cfg";
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
adsp: adsp@10680000 {
|
|
compatible = "mediatek,mt8186-dsp";
|
|
reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
|
|
<0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
|
|
reg-names = "cfg", "sram", "sec", "bus";
|
|
clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
|
|
clock-names = "audiodsp", "adsp_bus";
|
|
assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
|
|
<&topckgen CLK_TOP_ADSP_BUS>;
|
|
assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
|
|
mbox-names = "rx", "tx";
|
|
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adsp_mailbox0: mailbox@10686100 {
|
|
compatible = "mediatek,mt8186-adsp-mbox";
|
|
#mbox-cells = <0>;
|
|
reg = <0 0x10686100 0 0x1000>;
|
|
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
adsp_mailbox1: mailbox@10687100 {
|
|
compatible = "mediatek,mt8186-adsp-mbox";
|
|
#mbox-cells = <0>;
|
|
reg = <0 0x10687100 0 0x1000>;
|
|
interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
nor_flash: spi@11000000 {
|
|
compatible = "mediatek,mt8186-nor";
|
|
reg = <0 0x11000000 0 0x1000>;
|
|
clocks = <&topckgen CLK_TOP_SPINOR>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPINOR>,
|
|
<&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
|
|
<&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
|
|
clock-names = "spi", "sf", "axi", "axi_s";
|
|
assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
|
|
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
auxadc: adc@11001000 {
|
|
compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
|
|
clock-names = "main";
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,mt8186-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,mt8186-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@11007000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11007000 0 0x1000>,
|
|
<0 0x10200100 0 0x100>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11008000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11008000 0 0x1000>,
|
|
<0 0x10200200 0 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@11009000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11009000 0 0x1000>,
|
|
<0 0x10200300 0 0x180>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@1100f000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x1100f000 0 0x1000>,
|
|
<0 0x10200480 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@11011000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11011000 0 0x1000>,
|
|
<0 0x10200580 0 0x180>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@11016000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11016000 0 0x1000>,
|
|
<0 0x10200700 0 0x100>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@1100d000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x1100d000 0 0x1000>,
|
|
<0 0x10200800 0 0x100>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@11004000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11004000 0 0x1000>,
|
|
<0 0x10200900 0 0x180>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@11005000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11005000 0 0x1000>,
|
|
<0 0x10200A80 0 0x180>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@1100a000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI0>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
lvts: thermal-sensor@1100b000 {
|
|
compatible = "mediatek,mt8186-lvts";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
|
|
resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>;
|
|
nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
|
|
nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
svs: svs@1100bc00 {
|
|
compatible = "mediatek,mt8186-svs";
|
|
reg = <0 0x1100bc00 0 0x400>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
|
|
clock-names = "main";
|
|
nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>;
|
|
nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
|
|
resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>;
|
|
reset-names = "svs_rst";
|
|
};
|
|
|
|
pwm0: pwm@1100e000 {
|
|
compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&topckgen CLK_TOP_DISP_PWM>,
|
|
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@11010000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI1>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@11012000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI2>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@11013000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI3>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@11014000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI4>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@11015000 {
|
|
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_AO_SPI5>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
imp_iic_wrap: clock-controller@11017000 {
|
|
compatible = "mediatek,mt8186-imp_iic_wrap";
|
|
reg = <0 0x11017000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
uart2: serial@11018000 {
|
|
compatible = "mediatek,mt8186-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11018000 0 0x1000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@11019000 {
|
|
compatible = "mediatek,mt8186-i2c";
|
|
reg = <0 0x11019000 0 0x1000>,
|
|
<0 0x10200c00 0 0x180>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
|
|
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
afe: audio-controller@11210000 {
|
|
compatible = "mediatek,mt8186-sound";
|
|
reg = <0 0x11210000 0 0x2000>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
|
|
<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
|
|
<&topckgen CLK_TOP_AUDIO>,
|
|
<&topckgen CLK_TOP_AUD_INTBUS>,
|
|
<&topckgen CLK_TOP_MAINPLL_D2_D4>,
|
|
<&topckgen CLK_TOP_AUD_1>,
|
|
<&apmixedsys CLK_APMIXED_APLL1>,
|
|
<&topckgen CLK_TOP_AUD_2>,
|
|
<&apmixedsys CLK_APMIXED_APLL2>,
|
|
<&topckgen CLK_TOP_AUD_ENGEN1>,
|
|
<&topckgen CLK_TOP_APLL1_D8>,
|
|
<&topckgen CLK_TOP_AUD_ENGEN2>,
|
|
<&topckgen CLK_TOP_APLL2_D8>,
|
|
<&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
|
|
<&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
|
|
<&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
|
|
<&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
|
|
<&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
|
|
<&topckgen CLK_TOP_APLL12_CK_DIV0>,
|
|
<&topckgen CLK_TOP_APLL12_CK_DIV1>,
|
|
<&topckgen CLK_TOP_APLL12_CK_DIV2>,
|
|
<&topckgen CLK_TOP_APLL12_CK_DIV4>,
|
|
<&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
|
|
<&topckgen CLK_TOP_AUDIO_H>,
|
|
<&clk26m>;
|
|
clock-names = "aud_infra_clk",
|
|
"mtkaif_26m_clk",
|
|
"top_mux_audio",
|
|
"top_mux_audio_int",
|
|
"top_mainpll_d2_d4",
|
|
"top_mux_aud_1",
|
|
"top_apll1_ck",
|
|
"top_mux_aud_2",
|
|
"top_apll2_ck",
|
|
"top_mux_aud_eng1",
|
|
"top_apll1_d8",
|
|
"top_mux_aud_eng2",
|
|
"top_apll2_d8",
|
|
"top_i2s0_m_sel",
|
|
"top_i2s1_m_sel",
|
|
"top_i2s2_m_sel",
|
|
"top_i2s4_m_sel",
|
|
"top_tdm_m_sel",
|
|
"top_apll12_div0",
|
|
"top_apll12_div1",
|
|
"top_apll12_div2",
|
|
"top_apll12_div4",
|
|
"top_apll12_div_tdm",
|
|
"top_mux_audio_h",
|
|
"top_clk26m_clk";
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,apmixedsys = <&apmixedsys>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
mediatek,topckgen = <&topckgen>;
|
|
resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
|
|
reset-names = "audiosys";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusb0: usb@11201000 {
|
|
compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
|
|
reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
clocks = <&topckgen CLK_TOP_USB_TOP>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
|
|
<&infracfg_ao CLK_INFRA_AO_ICUSB>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
|
|
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
wakeup-source;
|
|
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
|
|
status = "disabled";
|
|
|
|
usb_host0: usb@11200000 {
|
|
compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x1000>;
|
|
reg-names = "mac";
|
|
clocks = <&topckgen CLK_TOP_USB_TOP>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
|
|
<&infracfg_ao CLK_INFRA_AO_ICUSB>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
|
|
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt8186-mmc",
|
|
"mediatek,mt8183-mmc";
|
|
reg = <0 0x11230000 0 0x10000>,
|
|
<0 0x11cd0000 0 0x1000>;
|
|
clocks = <&topckgen CLK_TOP_MSDC50_0>,
|
|
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
|
|
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
|
|
<&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
|
|
clock-names = "source", "hclk", "source_cg", "crypto";
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
|
|
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt8186-mmc",
|
|
"mediatek,mt8183-mmc";
|
|
reg = <0 0x11240000 0 0x1000>,
|
|
<0 0x11c90000 0 0x1000>;
|
|
clocks = <&topckgen CLK_TOP_MSDC30_1>,
|
|
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
|
|
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusb1: usb@11281000 {
|
|
compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
|
|
reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
|
|
<&clk26m>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
|
|
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
wakeup-source;
|
|
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
|
|
status = "disabled";
|
|
|
|
usb_host1: usb@11280000 {
|
|
compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x11280000 0 0x1000>;
|
|
reg-names = "mac";
|
|
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
|
|
<&clk26m>,
|
|
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
|
|
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
u3phy0: t-phy@11c80000 {
|
|
compatible = "mediatek,mt8186-tphy",
|
|
"mediatek,generic-tphy-v2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x11c80000 0x1000>;
|
|
status = "disabled";
|
|
|
|
u2port1: usb-phy@0 {
|
|
reg = <0x0 0x700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
u3port1: usb-phy@700 {
|
|
reg = <0x700 0x900>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
u3phy1: t-phy@11ca0000 {
|
|
compatible = "mediatek,mt8186-tphy",
|
|
"mediatek,generic-tphy-v2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x11ca0000 0x1000>;
|
|
status = "disabled";
|
|
|
|
u2port0: usb-phy@0 {
|
|
reg = <0x0 0x700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
mediatek,discth = <0x8>;
|
|
};
|
|
};
|
|
|
|
efuse: efuse@11cb0000 {
|
|
compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
|
|
reg = <0 0x11cb0000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
lvts_efuse_data1: lvts1-calib@1cc {
|
|
reg = <0x1cc 0x14>;
|
|
};
|
|
|
|
lvts_efuse_data2: lvts2-calib@2f8 {
|
|
reg = <0x2f8 0x14>;
|
|
};
|
|
|
|
svs_calibration: calib@550 {
|
|
reg = <0x550 0x50>;
|
|
};
|
|
|
|
gpu_speedbin: gpu-speedbin@59c {
|
|
reg = <0x59c 0x4>;
|
|
bits = <0 3>;
|
|
};
|
|
|
|
socinfo-data1@7a0 {
|
|
reg = <0x7a0 0x4>;
|
|
};
|
|
};
|
|
|
|
mipi_tx0: dsi-phy@11cc0000 {
|
|
compatible = "mediatek,mt8183-mipi-tx";
|
|
reg = <0 0x11cc0000 0 0x1000>;
|
|
clocks = <&clk26m>;
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
clock-output-names = "mipi_tx0_pll";
|
|
status = "disabled";
|
|
};
|
|
|
|
mfgsys: clock-controller@13000000 {
|
|
compatible = "mediatek,mt8186-mfgsys";
|
|
reg = <0 0x13000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpu: gpu@13040000 {
|
|
compatible = "mediatek,mt8186-mali",
|
|
"arm,mali-bifrost";
|
|
reg = <0 0x13040000 0 0x4000>;
|
|
|
|
clocks = <&mfgsys CLK_MFG_BG3D>;
|
|
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "job", "mmu", "gpu";
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
|
|
<&spm MT8186_POWER_DOMAIN_MFG3>;
|
|
power-domain-names = "core0", "core1";
|
|
#cooling-cells = <2>;
|
|
nvmem-cells = <&gpu_speedbin>;
|
|
nvmem-cell-names = "speed-bin";
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
dynamic-power-coefficient = <4687>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmsys: syscon@14000000 {
|
|
compatible = "mediatek,mt8186-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
|
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
|
};
|
|
|
|
mutex: mutex@14001000 {
|
|
compatible = "mediatek,mt8186-disp-mutex";
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
|
|
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
|
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
|
|
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
smi_common: smi@14002000 {
|
|
compatible = "mediatek,mt8186-smi-common";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
larb0: smi@14003000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <0>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
larb1: smi@14004000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <1>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
ovl0: ovl@14005000 {
|
|
compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
|
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
ovl_2l0: ovl@14006000 {
|
|
compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
|
|
reg = <0 0x14006000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
|
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
rdma0: rdma@14007000 {
|
|
compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
|
|
reg = <0 0x14007000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
color: color@14009000 {
|
|
compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
|
|
reg = <0 0x14009000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
|
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
dpi: dpi@1400a000 {
|
|
compatible = "mediatek,mt8186-dpi";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
clocks = <&topckgen CLK_TOP_DPI>,
|
|
<&mmsys CLK_MM_DISP_DPI>,
|
|
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
|
clock-names = "pixel", "engine", "pll";
|
|
assigned-clocks = <&topckgen CLK_TOP_DPI>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
|
|
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
status = "disabled";
|
|
|
|
port {
|
|
dpi_out: endpoint { };
|
|
};
|
|
};
|
|
|
|
ccorr: ccorr@1400b000 {
|
|
compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
|
|
reg = <0 0x1400b000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
|
|
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
aal: aal@1400c000 {
|
|
compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
|
|
reg = <0 0x1400c000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_AAL0>;
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
gamma: gamma@1400d000 {
|
|
compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
|
|
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
postmask: postmask@1400e000 {
|
|
compatible = "mediatek,mt8186-disp-postmask",
|
|
"mediatek,mt8192-disp-postmask";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
dither: dither@1400f000 {
|
|
compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
dsi0: dsi@14013000 {
|
|
compatible = "mediatek,mt8186-dsi";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DSI0>,
|
|
<&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
|
|
<&mipi_tx0>;
|
|
clock-names = "engine", "digital", "hs";
|
|
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
|
|
phys = <&mipi_tx0>;
|
|
phy-names = "dphy";
|
|
status = "disabled";
|
|
|
|
port {
|
|
dsi_out: endpoint { };
|
|
};
|
|
};
|
|
|
|
iommu_mm: iommu@14016000 {
|
|
compatible = "mediatek,mt8186-iommu-mm";
|
|
reg = <0 0x14016000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_SMI_IOMMU>;
|
|
clock-names = "bclk";
|
|
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
|
|
&larb7 &larb8 &larb9 &larb11
|
|
&larb13 &larb14 &larb16 &larb17
|
|
&larb19 &larb20>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
rdma1: rdma@1401f000 {
|
|
compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
|
|
reg = <0 0x1401f000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
|
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
|
|
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
wpesys: clock-controller@14020000 {
|
|
compatible = "mediatek,mt8186-wpesys";
|
|
reg = <0 0x14020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb8: smi@14023000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x14023000 0 0x1000>;
|
|
clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
|
|
<&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <8>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
|
|
};
|
|
|
|
imgsys1: clock-controller@15020000 {
|
|
compatible = "mediatek,mt8186-imgsys1";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb9: smi@1502e000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1502e000 0 0x1000>;
|
|
clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
|
|
<&imgsys1 CLK_IMG1_LARB9_IMG1>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <9>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
|
|
};
|
|
|
|
imgsys2: clock-controller@15820000 {
|
|
compatible = "mediatek,mt8186-imgsys2";
|
|
reg = <0 0x15820000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb11: smi@1582e000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1582e000 0 0x1000>;
|
|
clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
|
|
<&imgsys2 CLK_IMG2_LARB9_IMG2>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <11>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
|
|
};
|
|
|
|
video_decoder: video-decoder@16000000 {
|
|
compatible = "mediatek,mt8186-vcodec-dec";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>;
|
|
mediatek,scp = <&scp>;
|
|
|
|
vcodec_core: video-codec@16025000 {
|
|
compatible = "mediatek,mtk-vcodec-core";
|
|
reg = <0 0x16025000 0 0x1000>;
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
|
|
<&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>;
|
|
clocks = <&topckgen CLK_TOP_VDEC>,
|
|
<&vdecsys CLK_VDEC_CKEN>,
|
|
<&vdecsys CLK_VDEC_LARB1_CKEN>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3>;
|
|
clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
|
|
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
|
|
};
|
|
};
|
|
|
|
larb4: smi@1602e000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1602e000 0 0x1000>;
|
|
clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
|
|
<&vdecsys CLK_VDEC_LARB1_CKEN>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <4>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
vdecsys: clock-controller@1602f000 {
|
|
compatible = "mediatek,mt8186-vdecsys";
|
|
reg = <0 0x1602f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vencsys: clock-controller@17000000 {
|
|
compatible = "mediatek,mt8186-vencsys";
|
|
reg = <0 0x17000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb7: smi@17010000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
clocks = <&vencsys CLK_VENC_CKE1_VENC>,
|
|
<&vencsys CLK_VENC_CKE1_VENC>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <7>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
|
|
};
|
|
|
|
venc: video-encoder@17020000 {
|
|
compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
|
|
reg = <0 0x17020000 0 0x2000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_REC>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
|
|
clocks = <&vencsys CLK_VENC_CKE1_VENC>;
|
|
clock-names = "venc_sel";
|
|
assigned-clocks = <&topckgen CLK_TOP_VENC>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
|
|
mediatek,scp = <&scp>;
|
|
};
|
|
|
|
jpgenc: jpeg-encoder@17030000 {
|
|
compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";
|
|
reg = <0 0x17030000 0 0x10000>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&vencsys CLK_VENC_CKE2_JPGENC>;
|
|
clock-names = "jpgenc";
|
|
iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>,
|
|
<&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>,
|
|
<&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
|
|
};
|
|
|
|
camsys: clock-controller@1a000000 {
|
|
compatible = "mediatek,mt8186-camsys";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb13: smi@1a001000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1a001000 0 0x1000>;
|
|
clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <13>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
|
|
};
|
|
|
|
larb14: smi@1a002000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1a002000 0 0x1000>;
|
|
clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <14>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
|
|
};
|
|
|
|
larb16: smi@1a00f000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1a00f000 0 0x1000>;
|
|
clocks = <&camsys CLK_CAM_LARB14>,
|
|
<&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <16>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
|
|
};
|
|
|
|
larb17: smi@1a010000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1a010000 0 0x1000>;
|
|
clocks = <&camsys CLK_CAM_LARB13>,
|
|
<&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <17>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
|
|
};
|
|
|
|
camsys_rawa: clock-controller@1a04f000 {
|
|
compatible = "mediatek,mt8186-camsys_rawa";
|
|
reg = <0 0x1a04f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_rawb: clock-controller@1a06f000 {
|
|
compatible = "mediatek,mt8186-camsys_rawb";
|
|
reg = <0 0x1a06f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mdpsys: clock-controller@1b000000 {
|
|
compatible = "mediatek,mt8186-mdpsys";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb2: smi@1b002000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1b002000 0 0x1000>;
|
|
clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <2>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
|
};
|
|
|
|
ipesys: clock-controller@1c000000 {
|
|
compatible = "mediatek,mt8186-ipesys";
|
|
reg = <0 0x1c000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb20: smi@1c00f000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1c00f000 0 0x1000>;
|
|
clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <20>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
|
|
};
|
|
|
|
larb19: smi@1c10f000 {
|
|
compatible = "mediatek,mt8186-smi-larb";
|
|
reg = <0 0x1c10f000 0 0x1000>;
|
|
clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
|
|
clock-names = "apb", "smi";
|
|
mediatek,larb-id = <19>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
|
|
};
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
cpu-little0-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <150>;
|
|
thermal-sensors = <&lvts MT8186_LITTLE_CPU0>;
|
|
|
|
trips {
|
|
cpu_little0_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_little0_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpu_little0_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_little0_alert0>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-little1-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <150>;
|
|
thermal-sensors = <&lvts MT8186_LITTLE_CPU1>;
|
|
|
|
trips {
|
|
cpu_little1_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_little1_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpu_little1_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_little1_alert0>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-little2-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <150>;
|
|
thermal-sensors = <&lvts MT8186_LITTLE_CPU2>;
|
|
|
|
trips {
|
|
cpu_little2_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_little2_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpu_little2_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_little2_alert0>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cam-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&lvts MT8186_CAM>;
|
|
|
|
trips {
|
|
cam_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cam_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cam_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nna-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&lvts MT8186_NNA>;
|
|
|
|
trips {
|
|
nna_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
nna_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nna_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
adsp-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&lvts MT8186_ADSP>;
|
|
|
|
trips {
|
|
adsp_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
adsp_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
adsp_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&lvts MT8186_GPU>;
|
|
|
|
trips {
|
|
gpu_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
gpu_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
gpu_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-big0-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&lvts MT8186_BIG_CPU0>;
|
|
|
|
trips {
|
|
cpu_big0_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_big0_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpu_big0_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_big0_alert0>;
|
|
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-big1-thermal {
|
|
polling-delay = <1000>;
|
|
polling-delay-passive = <100>;
|
|
thermal-sensors = <&lvts MT8186_BIG_CPU1>;
|
|
|
|
trips {
|
|
cpu_big1_alert0: trip-alert0 {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_big1_alert1: trip-alert1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpu_big1_crit: trip-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_big1_alert0>;
|
|
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|