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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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3938bc6549
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value Edition LTE, a smartphone based on said SoC. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Link: https://lore.kernel.org/r/20250708-pxa1908-lkml-v16-4-b4392c484180@dujemihanovic.xyz Signed-off-by: Arnd Bergmann <arnd@arndb.de>
301 lines
6.9 KiB
Plaintext
301 lines
6.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/marvell,pxa1908.h>
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/ {
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model = "Marvell Armada PXA1908";
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compatible = "marvell,pxa1908";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 3>;
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enable-method = "psci";
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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smmu: iommu@c0010000 {
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compatible = "arm,mmu-400";
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reg = <0 0xc0010000 0 0x10000>;
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#global-interrupts = <1>;
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#iommu-cells = <1>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gic: interrupt-controller@d1df9000 {
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compatible = "arm,gic-400";
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reg = <0 0xd1df9000 0 0x1000>,
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<0 0xd1dfa000 0 0x2000>,
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/* The subsequent registers are guesses. */
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<0 0xd1dfc000 0 0x2000>,
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<0 0xd1dfe000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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apb@d4000000 {
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compatible = "simple-bus";
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reg = <0 0xd4000000 0 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xd4000000 0x200000>;
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pdma: dma-controller@0 {
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compatible = "marvell,pdma-1.0";
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reg = <0 0x10000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <30>;
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#dma-cells = <2>;
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};
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twsi1: i2c@10800 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10800 0x64>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbc PXA1908_CLK_TWSI1>;
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mrvl,i2c-fast-mode;
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status = "disabled";
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};
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twsi0: i2c@11000 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11000 0x64>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbc PXA1908_CLK_TWSI0>;
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mrvl,i2c-fast-mode;
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status = "disabled";
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};
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twsi3: i2c@13800 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x13800 0x64>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbc PXA1908_CLK_TWSI3>;
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mrvl,i2c-fast-mode;
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status = "disabled";
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};
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apbc: clock-controller@15000 {
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compatible = "marvell,pxa1908-apbc";
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reg = <0x15000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@17000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x17000 0x1000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbc PXA1908_CLK_UART0>;
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reg-shift = <2>;
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};
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uart1: serial@18000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x18000 0x1000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbc PXA1908_CLK_UART1>;
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reg-shift = <2>;
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};
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gpio: gpio@19000 {
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compatible = "marvell,mmp-gpio";
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reg = <0x19000 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&apbc PXA1908_CLK_GPIO>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpio_mux";
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges = <0 0x19000 0x800>;
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gpio@0 {
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reg = <0x0 0x4>;
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};
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gpio@4 {
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reg = <0x4 0x4>;
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};
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gpio@8 {
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reg = <0x8 0x4>;
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};
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gpio@100 {
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reg = <0x100 0x4>;
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};
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};
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pmx: pinmux@1e000 {
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compatible = "marvell,pxa1908-padconf", "pinconf-single";
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reg = <0x1e000 0x330>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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uart2: serial@36000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x36000 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbcp PXA1908_CLK_UART2>;
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reg-shift = <2>;
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};
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twsi2: i2c@37000 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x37000 0x64>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbcp PXA1908_CLK_TWSI2>;
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mrvl,i2c-fast-mode;
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status = "disabled";
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};
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apbcp: clock-controller@3b000 {
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compatible = "marvell,pxa1908-apbcp";
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reg = <0x3b000 0x1000>;
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#clock-cells = <1>;
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};
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mpmu: clock-controller@50000 {
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compatible = "marvell,pxa1908-mpmu";
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reg = <0x50000 0x1000>;
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#clock-cells = <1>;
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};
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};
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axi@d4200000 {
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compatible = "simple-bus";
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reg = <0 0xd4200000 0 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xd4200000 0x200000>;
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usbphy: phy@7000 {
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compatible = "marvell,pxa1928-usb-phy";
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reg = <0x7000 0x200>;
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clocks = <&apmu PXA1908_CLK_USB>;
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#phy-cells = <0>;
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};
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usb: usb@8000 {
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compatible = "chipidea,usb2";
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reg = <0x8000 0x200>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apmu PXA1908_CLK_USB>;
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phys = <&usbphy>;
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phy-names = "usb-phy";
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};
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sdh0: mmc@80000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0x80000 0x120>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apmu PXA1908_CLK_SDH0>;
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clock-names = "io";
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mrvl,clk-delay-cycles = <31>;
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};
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sdh1: mmc@80800 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0x80800 0x120>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apmu PXA1908_CLK_SDH1>;
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clock-names = "io";
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mrvl,clk-delay-cycles = <31>;
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};
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sdh2: mmc@81000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0x81000 0x120>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apmu PXA1908_CLK_SDH2>;
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clock-names = "io";
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mrvl,clk-delay-cycles = <31>;
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};
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apmu: clock-controller@82800 {
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compatible = "marvell,pxa1908-apmu";
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reg = <0x82800 0x400>;
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#clock-cells = <1>;
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};
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};
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};
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};
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