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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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859f3fac81
The Marvell .dtsi files define model and compatible properties which aren't complete. They are missing board compatible for example. This is mostly harmless as the properties will typically get overwritten. However, with these there will not be any warning should a board .dts forget to define its compatible and model. armada-371x.dtsi is not used anywhere, so it can be removed entirely since there is nothing left in it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada AP806.
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*/
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#include "armada-ap806.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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};
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};
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thermal-zones {
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/delete-node/ ap-thermal-cpu2;
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/delete-node/ ap-thermal-cpu3;
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};
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};
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