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f060fee24a
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The LG131x SoCs are missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Chanho Min <chanho.min@lge.com> Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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| .. | ||
| lg131x.dtsi | ||
| lg1312-ref.dts | ||
| lg1312.dtsi | ||
| lg1313-ref.dts | ||
| lg1313.dtsi | ||
| Makefile | ||