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ea89fdf24f
Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile phones. It features: * 4xA55 Little cluster * 2xA76 Mid cluster * 2xX1 Big cluster This commit adds the basic device tree for gs101 (SoC). Further platform support will be added over time. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-15-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
34 lines
870 B
C
34 lines
870 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Pinctrl binding constants for GS101
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*
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* Copyright 2020-2023 Google LLC
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*/
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#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
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#define __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
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#define GS101_PIN_PULL_NONE 0
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#define GS101_PIN_PULL_DOWN 1
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#define GS101_PIN_PULL_UP 3
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/* Pin function in power down mode */
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#define GS101_PIN_PDN_OUT0 0
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#define GS101_PIN_PDN_OUT1 1
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#define GS101_PIN_PDN_INPUT 2
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#define GS101_PIN_PDN_PREV 3
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/* GS101 drive strengths */
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#define GS101_PIN_DRV_2_5_MA 0
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#define GS101_PIN_DRV_5_MA 1
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#define GS101_PIN_DRV_7_5_MA 2
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#define GS101_PIN_DRV_10_MA 3
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#define GS101_PIN_FUNC_INPUT 0
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#define GS101_PIN_FUNC_OUTPUT 1
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#define GS101_PIN_FUNC_2 2
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#define GS101_PIN_FUNC_3 3
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#define GS101_PIN_FUNC_EINT 0xf
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#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__ */
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