mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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282cbd4360
These nodes were sorted by name, but it's nice to have the same class of devices together. As such, drop the pmu suffix and add "pmu" as a prefix. This keeps consistency between other Exynos SoCs too. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250105-pmu-sorting-v1-1-b55519eaff2e@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
330 lines
7.2 KiB
Plaintext
330 lines
7.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Samsung Exynos 990 SoC device tree source
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*
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* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
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*/
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#include <dt-bindings/clock/samsung,exynos990.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos990";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_cmgp;
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pinctrl2 = &pinctrl_hsi1;
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pinctrl3 = &pinctrl_hsi2;
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pinctrl4 = &pinctrl_peric0;
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pinctrl5 = &pinctrl_peric1;
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pinctrl6 = &pinctrl_vts;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x3>;
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enable-method = "psci";
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x4>;
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enable-method = "psci";
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x5>;
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enable-method = "psci";
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};
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cpu6: cpu@200 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m5";
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reg = <0x6>;
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enable-method = "psci";
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};
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cpu7: cpu@201 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m5";
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reg = <0x7>;
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enable-method = "psci";
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};
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};
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oscclk: clock-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "oscclk";
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};
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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pmu-a76 {
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compatible = "arm,cortex-a76-pmu";
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu4>,
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<&cpu5>;
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};
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pmu-mongoose-m5 {
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compatible = "samsung,mongoose-pmu";
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu6>,
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<&cpu7>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "hvc";
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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chipid@10000000 {
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compatible = "samsung,exynos990-chipid",
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"samsung,exynos850-chipid";
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reg = <0x10000000 0x100>;
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};
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cmu_peris: clock-controller@10020000 {
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compatible = "samsung,exynos990-cmu-peris";
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reg = <0x10020000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
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clock-names = "oscclk", "bus";
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};
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timer@10040000 {
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compatible = "samsung,exynos990-mct",
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"samsung,exynos4210-mct";
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reg = <0x10040000 0x800>;
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clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@10101000 {
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compatible = "arm,gic-400";
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reg = <0x10101000 0x1000>,
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<0x10102000 0x1000>,
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<0x10104000 0x2000>,
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<0x10106000 0x2000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_HIGH)>;
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#address-cells = <0>;
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#size-cells = <1>;
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};
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pinctrl_peric0: pinctrl@10430000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x10430000 0x1000>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_peric1: pinctrl@10730000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x10730000 0x1000>;
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interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_hsi0: clock-controller@10a00000 {
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compatible = "samsung,exynos990-cmu-hsi0";
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reg = <0x10a00000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
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<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
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clock-names = "oscclk",
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"bus",
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"usb31drd",
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"usbdp_debug",
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"dpgtc";
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};
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pinctrl_hsi1: pinctrl@13040000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x13040000 0x1000>;
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interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_hsi2: pinctrl@13c30000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x13c30000 0x1000>;
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interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_vts: pinctrl@15580000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x15580000 0x1000>;
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};
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pinctrl_alive: pinctrl@15850000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x15850000 0x1000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos990-wakeup-eint",
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"samsung,exynos850-wakeup-eint",
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"samsung,exynos7-wakeup-eint";
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};
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};
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pmu_system_controller: system-controller@15860000 {
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compatible = "samsung,exynos990-pmu",
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"samsung,exynos7-pmu", "syscon";
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reg = <0x15860000 0x10000>;
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x3a00>; /* SWRESET */
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mask = <0x2>; /* SWRESET_TRIGGER */
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value = <0x2>;
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};
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};
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pinctrl_cmgp: pinctrl@15c30000 {
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compatible = "samsung,exynos990-pinctrl";
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reg = <0x15c30000 0x1000>;
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};
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cmu_top: clock-controller@1a330000 {
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compatible = "samsung,exynos990-cmu-top";
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reg = <0x1a330000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>;
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clock-names = "oscclk";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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/*
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* Non-updatable, broken stock Samsung bootloader does not
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* configure CNTFRQ_EL0
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*/
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clock-frequency = <26000000>;
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};
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};
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#include "exynos990-pinctrl.dtsi"
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