mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 08:32:55 +00:00

Exynos 9810 is an ARMv8 mobile SoC found in various Samsung devices, such as Samsung Galaxy S9 (starlte), S9 Plus (star2lte), Note 9 (crownlte) and perhaps others. Add minimal support for this SoC, including basic stuff like: - PSCI for bringing up secondary cores - ARMv8 generic timer - GPIO and pinctrl. The firmware coming with the devices based on this SoC is buggy and doesn't configure CNTFRQ_EL0, as required by spec, so it's needed to hardcode the frequency in the timer node. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-1-4e91fbbc2133@gmail.com [krzysztof: Rename and move PMU nodes to proper sorting position] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
504 lines
8.8 KiB
Plaintext
504 lines
8.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
|
/*
|
|
* Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source
|
|
*
|
|
* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
|
|
* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
|
|
*/
|
|
|
|
#include "exynos-pinctrl.h"
|
|
|
|
&pinctrl_alive {
|
|
etc1: etc1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpa0: gpa0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpa1: gpa1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpa2: gpa2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpa3: gpa3-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpa4: gpa4-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpq0: gpq0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_aud {
|
|
gpb0: gpb0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpb1: gpb1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpb2: gpb2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_chub {
|
|
gph0: gph0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gph1: gph1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_cmgp {
|
|
gpm0: gpm0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm1: gpm1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm2: gpm2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm3: gpm3-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm4: gpm4-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm5: gpm5-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm6: gpm6-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm7: gpm7-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm10: gpm10-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm11: gpm11-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm12: gpm12-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm13: gpm13-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm14: gpm14-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm15: gpm15-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm16: gpm16-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm17: gpm17-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm40: gpm40-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm41: gpm41-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm42: gpm42-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gpm43: gpm43-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_fsys0 {
|
|
gpf0: gpf0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_fsys1 {
|
|
gpf1: gpf1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpf2: gpf2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_peric0 {
|
|
gpg0: gpg0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpg1: gpg1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpg2: gpg2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp0: gpp0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp1: gpp1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp2: gpp2-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp3: gpp3-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_peric1 {
|
|
gpc0: gpc0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpc1: gpc1-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpd0: gpd0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpg3: gpg3-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp4: gpp4-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp5: gpp5-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpp6: gpp6-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_vts {
|
|
gpt0: gpt0-gpio-bank {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|