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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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11715fcf1c
Exynos 2200 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy S22 (r0s), S22+ (g0s), S22 Ultra (b0s) Add minimal support for that SoC, including psci, pmu, chipid, architecture timer and mct, pinctrl, clocks and usb. The devices using this SoC suffer from an issue caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Further platform support will be added over time. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250504145907.1728721-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
562 lines
13 KiB
Plaintext
562 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Samsung's Exynos 2200 SoC device tree source
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*
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* Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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*/
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#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos2200";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_cmgp;
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pinctrl2 = &pinctrl_hsi1;
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pinctrl3 = &pinctrl_ufs;
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pinctrl4 = &pinctrl_hsi1ufs;
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pinctrl5 = &pinctrl_peric0;
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pinctrl6 = &pinctrl_peric1;
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pinctrl7 = &pinctrl_peric2;
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pinctrl8 = &pinctrl_vts;
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};
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xtcxo: clock-1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "oscclk";
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};
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ext_26m: clock-2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ext-26m";
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};
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ext_200m: clock-3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ext-200m";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a510";
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reg = <0>;
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capacity-dmips-mhz = <260>;
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dynamic-power-coefficient = <189>;
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enable-method = "psci";
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cpu-idle-states = <&little_cpu_sleep>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a510";
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reg = <0x100>;
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capacity-dmips-mhz = <260>;
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dynamic-power-coefficient = <189>;
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enable-method = "psci";
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cpu-idle-states = <&little_cpu_sleep>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a510";
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reg = <0x200>;
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capacity-dmips-mhz = <260>;
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dynamic-power-coefficient = <189>;
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enable-method = "psci";
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cpu-idle-states = <&little_cpu_sleep>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a510";
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reg = <0x300>;
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capacity-dmips-mhz = <260>;
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dynamic-power-coefficient = <189>;
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enable-method = "psci";
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cpu-idle-states = <&little_cpu_sleep>;
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a710";
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reg = <0x400>;
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capacity-dmips-mhz = <380>;
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dynamic-power-coefficient = <560>;
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enable-method = "psci";
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cpu-idle-states = <&big_cpu_sleep>;
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a710";
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reg = <0x500>;
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capacity-dmips-mhz = <380>;
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dynamic-power-coefficient = <560>;
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enable-method = "psci";
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cpu-idle-states = <&big_cpu_sleep>;
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a710";
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reg = <0x600>;
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capacity-dmips-mhz = <380>;
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dynamic-power-coefficient = <560>;
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enable-method = "psci";
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cpu-idle-states = <&big_cpu_sleep>;
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-x2";
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reg = <0x700>;
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capacity-dmips-mhz = <488>;
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dynamic-power-coefficient = <765>;
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enable-method = "psci";
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cpu-idle-states = <&prime_cpu_sleep>;
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};
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idle-states {
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entry-method = "psci";
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little_cpu_sleep: cpu-sleep-0 {
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compatible = "arm,idle-state";
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idle-state-name = "c2";
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entry-latency-us = <70>;
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exit-latency-us = <170>;
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min-residency-us = <2000>;
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arm,psci-suspend-param = <0x10000>;
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};
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big_cpu_sleep: cpu-sleep-1 {
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compatible = "arm,idle-state";
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idle-state-name = "c2";
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entry-latency-us = <235>;
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exit-latency-us = <220>;
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min-residency-us = <3500>;
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arm,psci-suspend-param = <0x10000>;
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};
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prime_cpu_sleep: cpu-sleep-2 {
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compatible = "arm,idle-state";
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idle-state-name = "c2";
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entry-latency-us = <150>;
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exit-latency-us = <190>;
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min-residency-us = <2500>;
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arm,psci-suspend-param = <0x10000>;
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};
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};
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};
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pmu-a510 {
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compatible = "arm,cortex-a510-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
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};
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pmu-a710 {
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compatible = "arm,cortex-a710-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
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};
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pmu-x2 {
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compatible = "arm,cortex-x2-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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chipid@10000000 {
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compatible = "samsung,exynos2200-chipid",
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"samsung,exynos850-chipid";
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reg = <0x0 0x10000000 0x0 0x24>;
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};
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cmu_peris: clock-controller@10020000 {
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compatible = "samsung,exynos2200-cmu-peris";
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reg = <0x0 0x10020000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>,
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<&cmu_top CLK_DOUT_CMU_PERIS_NOC>,
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<&cmu_top CLK_DOUT_CMU_PERIS_GIC>;
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clock-names = "tcxo_div3",
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"noc",
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"gic";
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};
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mct_peris: timer@10040000 {
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compatible = "samsung,exynos2200-mct-peris",
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"samsung,exynos4210-mct";
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reg = <0x0 0x10040000 0x0 0x800>;
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clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 947 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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gic: interrupt-controller@10200000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */
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<0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */
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#interrupt-cells = <4>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu4 &cpu5 &cpu6>;
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};
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ppi_cluster2: interrupt-partition-2 {
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affinity = <&cpu7>;
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};
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};
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};
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cmu_peric0: clock-controller@10400000 {
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compatible = "samsung,exynos2200-cmu-peric0";
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reg = <0x0 0x10400000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_NOC>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_IP0>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_IP1>;
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clock-names = "oscclk", "noc", "ip0", "ip1";
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};
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syscon_peric0: syscon@10420000 {
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compatible = "samsung,exynos2200-peric0-sysreg", "syscon";
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reg = <0x0 0x10420000 0x0 0x2000>;
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};
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pinctrl_peric0: pinctrl@10430000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x10430000 0x0 0x1000>;
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};
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cmu_peric1: clock-controller@10700000 {
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compatible = "samsung,exynos2200-cmu-peric1";
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reg = <0x0 0x10700000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_NOC>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_IP0>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_IP1>;
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clock-names = "oscclk", "noc", "ip0", "ip1";
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};
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syscon_peric1: syscon@10720000 {
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compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
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reg = <0x0 0x10720000 0x0 0x2000>;
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};
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pinctrl_peric1: pinctrl@10730000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x10730000 0x0 0x1000>;
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};
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cmu_hsi0: clock-controller@10a00000 {
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compatible = "samsung,exynos2200-cmu-hsi0";
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reg = <0x0 0x10a00000 0x0 0x8000>;
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#clock-cells = <1>;
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};
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usb32drd: phy@10aa0000 {
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compatible = "samsung,exynos2200-usb32drd-phy";
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reg = <0x0 0x10aa0000 0x0 0x10000>;
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clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
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clock-names = "phy";
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#phy-cells = <1>;
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phys = <&usb_hsphy>;
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phy-names = "hs";
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samsung,pmu-syscon = <&pmu_system_controller>;
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status = "disabled";
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};
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usb_hsphy: phy@10ab0000 {
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compatible = "samsung,exynos2200-eusb2-phy";
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reg = <0x0 0x10ab0000 0x0 0x10000>;
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clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>,
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<&cmu_hsi0 CLK_MOUT_HSI0_NOC>,
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<&cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB>;
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clock-names = "ref", "bus", "ctrl";
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#phy-cells = <0>;
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status = "disabled";
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};
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usb: usb@10b00000 {
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compatible = "samsung,exynos2200-dwusb3";
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ranges = <0x0 0x0 0x10b00000 0x10000>;
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clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
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clock-names = "link_aclk";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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usb_dwc3: usb@0 {
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compatible = "snps,dwc3";
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reg = <0x0 0x10000>;
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clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>;
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clock-names = "ref";
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interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH 0>;
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phys = <&usb32drd 0>;
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phy-names = "usb2-phy";
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snps,dis-u2-freeclk-exists-quirk;
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snps,gfladj-refclk-lpm-sel-quirk;
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snps,has-lpm-erratum;
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,usb3_lpm_capable;
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};
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};
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cmu_ufs: clock-controller@11000000 {
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compatible = "samsung,exynos2200-cmu-ufs";
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reg = <0x0 0x11000000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top CLK_DOUT_CMU_UFS_NOC>,
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<&cmu_top CLK_MOUT_CMU_UFS_MMC_CARD>,
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<&cmu_top CLK_DOUT_CMU_UFS_UFS_EMBD>;
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clock-names = "oscclk", "noc", "mmc", "ufs";
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};
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syscon_ufs: syscon@11020000 {
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compatible = "samsung,exynos2200-ufs-sysreg", "syscon";
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reg = <0x0 0x11020000 0x0 0x2000>;
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};
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pinctrl_ufs: pinctrl@11040000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x11040000 0x0 0x1000>;
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};
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pinctrl_hsi1ufs: pinctrl@11060000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x11060000 0x0 0x1000>;
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};
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pinctrl_hsi1: pinctrl@11240000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x11240000 0x0 0x1000>;
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};
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cmu_peric2: clock-controller@11c00000 {
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compatible = "samsung,exynos2200-cmu-peric2";
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reg = <0x0 0x11c00000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top CLK_DOUT_CMU_PERIC2_NOC>,
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<&cmu_top CLK_DOUT_CMU_PERIC2_IP0>,
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<&cmu_top CLK_DOUT_CMU_PERIC2_IP1>;
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clock-names = "oscclk", "noc", "ip0", "ip1";
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};
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syscon_peric2: syscon@11c20000 {
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compatible = "samsung,exynos2200-peric2-sysreg", "syscon";
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reg = <0x0 0x11c20000 0x0 0x4000>;
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};
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pinctrl_peric2: pinctrl@11c30000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x11c30000 0x0 0x1000>;
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};
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cmu_cmgp: clock-controller@14e00000 {
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compatible = "samsung,exynos2200-cmu-cmgp";
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reg = <0x0 0x14e00000 0x0 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_alive CLK_DOUT_ALIVE_CMGP_NOC>,
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<&cmu_alive CLK_DOUT_ALIVE_CMGP_PERI>;
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clock-names = "oscclk", "noc", "peri";
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};
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syscon_cmgp: syscon@14e20000 {
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compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
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reg = <0x0 0x14e20000 0x0 0x2000>;
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};
|
|
|
|
pinctrl_cmgp: pinctrl@14e30000 {
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compatible = "samsung,exynos2200-pinctrl";
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reg = <0x0 0x14e30000 0x0 0x1000>;
|
|
|
|
wakeup-interrupt-controller {
|
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compatible = "samsung,exynos2200-wakeup-eint",
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|
"samsung,exynos850-wakeup-eint",
|
|
"samsung,exynos7-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
cmu_vts: clock-controller@15300000 {
|
|
compatible = "samsung,exynos2200-cmu-vts";
|
|
reg = <0x0 0x15300000 0x0 0x8000>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&xtcxo>,
|
|
<&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
|
|
clock-names = "oscclk", "dmic";
|
|
};
|
|
|
|
pinctrl_vts: pinctrl@15320000 {
|
|
compatible = "samsung,exynos2200-pinctrl";
|
|
reg = <0x0 0x15320000 0x0 0x1000>;
|
|
};
|
|
|
|
cmu_alive: clock-controller@15800000 {
|
|
compatible = "samsung,exynos2200-cmu-alive";
|
|
reg = <0x0 0x15800000 0x0 0x8000>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&xtcxo>,
|
|
<&cmu_top CLK_DOUT_CMU_ALIVE_NOC>;
|
|
clock-names = "oscclk", "noc";
|
|
};
|
|
|
|
pinctrl_alive: pinctrl@15850000 {
|
|
compatible = "samsung,exynos2200-pinctrl";
|
|
reg = <0x0 0x15850000 0x0 0x1000>;
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos2200-wakeup-eint",
|
|
"samsung,exynos850-wakeup-eint",
|
|
"samsung,exynos7-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
pmu_system_controller: system-controller@15860000 {
|
|
compatible = "samsung,exynos2200-pmu",
|
|
"samsung,exynos7-pmu", "syscon";
|
|
reg = <0x0 0x15860000 0x0 0x10000>;
|
|
|
|
reboot: syscon-reboot {
|
|
compatible = "syscon-reboot";
|
|
offset = <0x3c00>; /* SYSTEM_CONFIGURATION */
|
|
mask = <0x2>; /* SWRESET_SYSTEM */
|
|
value = <0x2>; /* reset value */
|
|
};
|
|
};
|
|
|
|
cmu_top: clock-controller@1a320000 {
|
|
compatible = "samsung,exynos2200-cmu-top";
|
|
reg = <0x0 0x1a320000 0x0 0x8000>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&xtcxo>;
|
|
clock-names = "oscclk";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
|
|
/*
|
|
* Non-updatable, broken stock Samsung bootloader does not
|
|
* configure CNTFRQ_EL0
|
|
*/
|
|
clock-frequency = <25600000>;
|
|
};
|
|
};
|
|
|
|
#include "exynos2200-pinctrl.dtsi"
|