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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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80be23bb20
CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, and Orion O6 is the motherboard launched by Radxa. See below for detail: https://docs.radxa.com/en/orion/o6/getting-started/introduction In this commit, it only adds limited components for running initramfs at Orion O6. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com> Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
331 lines
7.3 KiB
Plaintext
331 lines
7.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2025 Cix Technology Group Co., Ltd.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/cix,sky1.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x0>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x100>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x200>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x300>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu4: cpu@400 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x400>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu5: cpu@500 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x500>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu6: cpu@600 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x600>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu7: cpu@700 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x700>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu8: cpu@800 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x800>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu9: cpu@900 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x900>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu10: cpu@a00 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0xa00>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu11: cpu@b00 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0xb00>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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core8 {
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cpu = <&cpu8>;
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};
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core9 {
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cpu = <&cpu9>;
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};
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core10 {
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cpu = <&cpu10>;
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};
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core11 {
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cpu = <&cpu11>;
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};
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};
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};
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};
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firmware {
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ap_to_pm_scmi: scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
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shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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pmu-a520 {
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compatible = "arm,cortex-a520-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
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};
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pmu-a720 {
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compatible = "arm,cortex-a720-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0 0x20 0>;
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dma-ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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uart0: serial@40b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040b0000 0x0 0x1000>;
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interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@40c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040c0000 0x0 0x1000>;
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interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@40d0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040d0000 0x0 0x1000>;
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interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart3: serial@40e0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040e0000 0x0 0x1000>;
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interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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mbox_ap2se: mailbox@5060000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x05060000 0x0 0x10000>;
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interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "tx";
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};
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mbox_se2ap: mailbox@5070000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x05070000 0x0 0x10000>;
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interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "rx";
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};
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ap2pm_scmi_mem: shmem@6590000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x06590000 0x0 0x80>;
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reg-io-width = <4>;
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};
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mbox_ap2pm: mailbox@6590080 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x06590080 0x0 0xff80>;
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interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "tx";
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};
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pm2ap_scmi_mem: shmem@65a0000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x065a0000 0x0 0x80>;
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reg-io-width = <4>;
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};
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mbox_pm2ap: mailbox@65a0080 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x065a0080 0x0 0xff80>;
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interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "rx";
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};
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mbox_sfh2ap: mailbox@8090000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x08090000 0x0 0x10000>;
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interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "rx";
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};
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mbox_ap2sfh: mailbox@80a0000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x080a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "tx";
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};
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gic: interrupt-controller@e010000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
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<0x0 0x0e090000 0 0x300000>; /* GICR * 12 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
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#interrupt-cells = <4>;
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interrupt-controller;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic_its: msi-controller@e050000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x0e050000 0x0 0x30000>;
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msi-controller;
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#msi-cells = <1>;
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};
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ppi-partitions {
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ppi_partition0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_partition1: interrupt-partition-1 {
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affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
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};
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};
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