mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-29 19:49:10 +00:00
0d495db1b9
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The Thunder2 SoC is missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250609215706.3009692-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| thunder2-99xx.dts | ||
| thunder2-99xx.dtsi | ||
| thunder-88xx.dts | ||
| thunder-88xx.dtsi | ||