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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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eed7414420
RaspberryPi RP1 is a multi function PCI endpoint device that exposes several subperipherals via PCI BAR. Add a dtb overlay that will be compiled into a binary blob and linked in the RP1 driver. This overlay offers just minimal support to represent the RP1 device itself, the sub-peripherals will be added by future patches. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-6-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
43 lines
1.3 KiB
Plaintext
43 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
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pci_ep_bus: pci-ep-bus@1 {
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compatible = "simple-bus";
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ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
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dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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rp1_clocks: clocks@40018000 {
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compatible = "raspberrypi,rp1-clocks";
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reg = <0x00 0x40018000 0x0 0x10038>;
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#clock-cells = <1>;
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clocks = <&clk_rp1_xosc>;
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assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>,
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<&rp1_clocks RP1_PLL_SYS>,
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<&rp1_clocks RP1_PLL_SYS_SEC>,
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<&rp1_clocks RP1_CLK_SYS>;
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assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE
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<200000000>, // RP1_PLL_SYS
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<125000000>, // RP1_PLL_SYS_SEC
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<200000000>; // RP1_CLK_SYS
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};
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rp1_gpio: pinctrl@400d0000 {
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compatible = "raspberrypi,rp1-gpio";
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reg = <0x00 0x400d0000 0x0 0xc000>,
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<0x00 0x400e0000 0x0 0xc000>,
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<0x00 0x400f0000 0x0 0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
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<1 IRQ_TYPE_LEVEL_HIGH>,
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<2 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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