linux-loongson/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
Linus Torvalds 78c3925c04 ARM: late SoC changes for 6.9
These are changes that for some reason ended up not making it into the
 first four branches but that should still make it into 6.9:
 
  - A rework of the omap clock support that touches both drivers and
    device tree files
 
  - The reset controller branch changes that had a dependency on late
    bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
    drivers branch
 
  - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
    changes that got delayed and needed some extra time in linux-next
    for wider testing.
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Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull more ARM SoC updates from Arnd Bergmann:
 "These are changes that for some reason ended up not making it into the
  first four branches but that should still make it into 6.9:

   - A rework of the omap clock support that touches both drivers and
     device tree files

   - The reset controller branch changes that had a dependency on late
     bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
     drivers branch

   - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
     changes that got delayed and needed some extra time in linux-next
     for wider testing"

* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
  soc: fsl: dpio: fix kcalloc() argument order
  bus: ts-nbus: Improve error reporting
  bus: ts-nbus: Convert to atomic pwm API
  riscv: dts: starfive: jh7110: Add camera subsystem nodes
  ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
  ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
  ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
  clk: ti: Improve clksel clock bit parsing for reg property
  clk: ti: Handle possible address in the node name
  dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
  dt-bindings: riscv: cpus: reg matches hart ID
  reset: Instantiate reset GPIO controller for shared reset-gpios
  reset: gpio: Add GPIO-based reset controller
  cpufreq: do not open-code of_phandle_args_equal()
  of: Add of_phandle_args_equal() helper
  reset: simple: add support for Sophgo SG2042
  dt-bindings: reset: sophgo: support SG2042
  riscv: dts: microchip: add specific compatible for mpfs pdma
  riscv: dts: microchip: add missing CAN bus clocks
  ARM: brcmstb: Add debug UART entry for 74165
  ...
2024-03-19 11:57:26 -07:00

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Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "bcm4908.dtsi"
/ {
compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
model = "Asus GT-AC5300";
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x40000000>;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <100>;
key-wifi {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
key-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
key-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
};
key-brightness {
label = "LEDs";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
};
};
};
&enet {
nvmem-cells = <&base_mac_addr>;
nvmem-cell-names = "mac-address";
};
&usb_phy {
brcm,ioc = <1>;
status = "okay";
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&xhci {
status = "okay";
};
&ports {
port@0 {
label = "lan2";
};
port@1 {
label = "lan1";
};
port@2 {
label = "lan6";
};
port@3 {
label = "lan5";
};
/* External BCM53134S switch */
port@7 {
label = "sw";
reg = <7>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
&mdio {
/* lan8 */
ethernet-phy@0 {
reg = <0>;
};
/* lan7 */
ethernet-phy@1 {
reg = <1>;
};
/* lan4 */
ethernet-phy@2 {
reg = <2>;
};
/* lan3 */
ethernet-phy@3 {
reg = <3>;
};
};
&leds {
led@11 {
reg = <0x11>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
default-state = "on";
active-low;
pinctrl-names = "default";
pinctrl-0 = <&pins_led_17_a>;
};
led@12 {
reg = <0x12>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_RED>;
active-low;
pinctrl-names = "default";
pinctrl-0 = <&pins_led_18_a>;
};
led@14 {
reg = <0x14>;
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_WHITE>;
active-low;
pinctrl-names = "default";
pinctrl-0 = <&pins_led_20_a>;
};
led@15 {
reg = <0x15>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
active-low;
pinctrl-names = "default";
pinctrl-0 = <&pins_led_21_a>;
};
led@19 {
reg = <0x19>;
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_WHITE>;
pinctrl-names = "default";
pinctrl-0 = <&pins_led_25_a>;
};
};
&nand_controller {
brcm,wp-not-connected;
status = "okay";
};
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
partitions {
compatible = "brcm,bcm4908-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "cferom";
reg = <0x0 0x100000>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
base_mac_addr: mac@106a0 {
reg = <0x106a0 0x6>;
};
};
};
partition@100000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x100000 0x5700000>;
};
partition@5800000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x5800000 0x5700000>;
};
};
};