mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 15:14:52 +00:00
c9e81198a7
There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/all/20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org/ Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
614 lines
17 KiB
Plaintext
614 lines
17 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm2712";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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clocks {
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/* The oscillator is the root of the clock tree. */
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clk_osc: clk-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "osc";
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clock-frequency = <54000000>;
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};
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clk_vpu: clk-vpu {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <750000000>;
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clock-output-names = "vpu-clock";
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};
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clk_uart: clk-uart {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <9216000>;
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clock-output-names = "uart-clock";
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};
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clk_emmc2: clk-emmc2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "emmc2-clock";
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};
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Source for L1 d/i cache-line-size, cache-sets, cache-size
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* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
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* Source for L2 cache-line-size and cache-sets:
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* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
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* and for cache-size:
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* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
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*/
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x000>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l0>;
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l2_cache_l0: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l1>;
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l2_cache_l1: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l2>;
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l2_cache_l2: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l3>;
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l2_cache_l3: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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/* Source for cache-line-size and cache-sets:
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* https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
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* Source for cache-size:
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* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
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*/
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l3_cache: l3-cache {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
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cache-level = <3>;
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cache-unified;
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};
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};
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psci {
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method = "smc";
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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};
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rmem: reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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atf@0 {
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reg = <0x0 0x0 0x0 0x80000>;
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no-map;
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};
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cma: linux,cma {
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compatible = "shared-dma-pool";
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size = <0x0 0x4000000>; /* 64MB */
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reusable;
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linux,cma-default;
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alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
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};
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};
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soc: soc@107c000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x10 0x00000000 0x80000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pcie_rescal: reset-controller@119500 {
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compatible = "brcm,bcm7216-pcie-sata-rescal";
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reg = <0x00119500 0x10>;
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#reset-cells = <0>;
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};
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sdio1: mmc@fff000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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reg = <0x00fff000 0x260>,
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<0x00fff400 0x200>;
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reg-names = "host", "cfg";
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interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_emmc2>;
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clock-names = "sw_sdio";
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mmc-ddr-3_3v;
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};
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bcm_reset: reset-controller@1504318 {
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compatible = "brcm,brcmstb-reset";
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reg = <0x01504318 0x30>;
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#reset-cells = <1>;
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};
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system_timer: timer@7c003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7c003000 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1000000>;
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};
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mailbox: mailbox@7c013880 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7c013880 0x40>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <0>;
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};
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uart10: serial@7d001000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7d001000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_uart>, <&clk_vpu>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00341011>;
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status = "disabled";
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};
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interrupt-controller@7d517000 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d517000 0x10>;
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interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gio_aon: gpio@7d517c00 {
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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reg = <0x7d517c00 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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brcm,gpio-bank-widths = <17 6>;
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/* The lack of 'interrupt-controller' property here is intended:
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* don't use GIO_AON as an interrupt controller because it will
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* clash with the firmware monitoring the PMIC interrupt via the VPU.
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*/
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};
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gicv2: interrupt-controller@7fff9000 {
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compatible = "arm,gic-400";
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reg = <0x7fff9000 0x1000>,
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<0x7fffa000 0x2000>,
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<0x7fffc000 0x2000>,
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<0x7fffe000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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aon_intr: interrupt-controller@7d510600 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7d510600 0x30>;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pixelvalve0: pixelvalve@7c410000 {
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compatible = "brcm,bcm2712-pixelvalve0";
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reg = <0x7c410000 0x100>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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};
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pixelvalve1: pixelvalve@7c411000 {
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compatible = "brcm,bcm2712-pixelvalve1";
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reg = <0x7c411000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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};
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mop: mop@7c500000 {
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compatible = "brcm,bcm2712-mop";
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reg = <0x7c500000 0x28>;
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interrupt-parent = <&disp_intr>;
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interrupts = <1>;
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};
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moplet: moplet@7c501000 {
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compatible = "brcm,bcm2712-moplet";
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reg = <0x7c501000 0x20>;
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interrupt-parent = <&disp_intr>;
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interrupts = <0>;
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};
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disp_intr: interrupt-controller@7c502000 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7c502000 0x30>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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dvp: clock@7c700000 {
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compatible = "brcm,brcm2711-dvp";
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reg = <0x7c700000 0x10>;
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clocks = <&clk_108MHz>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ddc0: i2c@7d508200 {
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compatible = "brcm,brcmstb-i2c";
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reg = <0x7d508200 0x58>;
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interrupt-parent = <&bsc_irq>;
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interrupts = <1>;
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clock-frequency = <97500>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ddc1: i2c@7d508280 {
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compatible = "brcm,brcmstb-i2c";
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reg = <0x7d508280 0x58>;
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interrupt-parent = <&bsc_irq>;
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interrupts = <2>;
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clock-frequency = <97500>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bsc_irq: interrupt-controller@7d508380 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d508380 0x10>;
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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main_irq: interrupt-controller@7d508400 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d508400 0x10>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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hdmi0: hdmi@7c701400 {
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compatible = "brcm,bcm2712-hdmi0";
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reg = <0x7c701400 0x300>,
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<0x7c701000 0x200>,
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<0x7c701d00 0x300>,
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<0x7c702000 0x80>,
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<0x7c703800 0x200>,
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<0x7c704000 0x800>,
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<0x7c700100 0x80>,
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<0x7d510800 0x100>,
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<0x7c720000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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resets = <&dvp 1>;
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interrupt-parent = <&aon_intr>;
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interrupts = <1>, <2>, <3>,
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<7>, <8>;
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interrupt-names = "cec-tx", "cec-rx", "cec-low",
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"hpd-connected", "hpd-removed";
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ddc = <&ddc0>;
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};
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hdmi1: hdmi@7c706400 {
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compatible = "brcm,bcm2712-hdmi1";
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reg = <0x7c706400 0x300>,
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<0x7c706000 0x200>,
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<0x7c706d00 0x300>,
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<0x7c707000 0x80>,
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<0x7c708800 0x200>,
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<0x7c709000 0x800>,
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<0x7c700180 0x80>,
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<0x7d511000 0x100>,
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<0x7c720000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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resets = <&dvp 2>;
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interrupt-parent = <&aon_intr>;
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interrupts = <11>, <12>, <13>,
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<14>, <15>;
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interrupt-names = "cec-tx", "cec-rx", "cec-low",
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"hpd-connected", "hpd-removed";
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ddc = <&ddc1>;
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};
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};
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axi: axi {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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vc4: gpu {
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compatible = "brcm,bcm2712-vc6";
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};
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pcie0: pcie@1000100000 {
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compatible = "brcm,bcm2712-pcie";
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reg = <0x10 0x00100000 0x00 0x9310>;
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device_type = "pci";
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linux,pci-domain = <0>;
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max-link-speed = <2>;
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num-lanes = <1>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&pcie_rescal>, <&bcm_reset 42>;
|
|
reset-names = "rescal", "bridge";
|
|
msi-controller;
|
|
msi-parent = <&pcie0>;
|
|
|
|
ranges =
|
|
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
|
|
<0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
|
|
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
|
|
<0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
|
|
|
|
dma-ranges =
|
|
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
|
|
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@1000110000 {
|
|
compatible = "brcm,bcm2712-pcie";
|
|
reg = <0x10 0x00110000 0x00 0x9310>;
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
max-link-speed = <2>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gicv2>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pcie", "msi";
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&pcie_rescal>, <&bcm_reset 43>;
|
|
reset-names = "rescal", "bridge";
|
|
msi-controller;
|
|
msi-parent = <&mip1>;
|
|
|
|
ranges =
|
|
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
|
|
<0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
|
|
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
|
|
<0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
|
|
|
|
dma-ranges =
|
|
/* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
|
|
<0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
|
|
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
|
|
<0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2: pcie@1000120000 {
|
|
compatible = "brcm,bcm2712-pcie";
|
|
reg = <0x10 0x00120000 0x00 0x9310>;
|
|
device_type = "pci";
|
|
linux,pci-domain = <2>;
|
|
max-link-speed = <2>;
|
|
num-lanes = <4>;
|
|
#address-cells = <3>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gicv2>;
|
|
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pcie", "msi";
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&pcie_rescal>, <&bcm_reset 44>;
|
|
reset-names = "rescal", "bridge";
|
|
msi-controller;
|
|
msi-parent = <&mip0>;
|
|
|
|
ranges =
|
|
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
|
|
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
|
|
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
|
|
<0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
|
|
|
|
dma-ranges =
|
|
/* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
|
|
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
|
|
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
|
|
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
|
|
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
|
|
<0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mip0: msi-controller@1000130000 {
|
|
compatible = "brcm,bcm2712-mip";
|
|
reg = <0x10 0x00130000 0x00 0xc0>,
|
|
<0xff 0xfffff000 0x00 0x1000>;
|
|
msi-controller;
|
|
msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
|
|
brcm,msi-offset = <0>;
|
|
};
|
|
|
|
mip1: msi-controller@1000131000 {
|
|
compatible = "brcm,bcm2712-mip";
|
|
reg = <0x10 0x00131000 0x00 0xc0>,
|
|
<0xff 0xfffff000 0x00 0x1000>;
|
|
msi-controller;
|
|
msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
|
|
brcm,msi-offset = <8>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
clk_27MHz: clk-27M {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <27000000>;
|
|
clock-output-names = "27MHz-clock";
|
|
};
|
|
|
|
clk_108MHz: clk-108M {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <108000000>;
|
|
clock-output-names = "108MHz-clock";
|
|
};
|
|
|
|
hvs: hvs@107c580000 {
|
|
compatible = "brcm,bcm2712-hvs";
|
|
reg = <0x10 0x7c580000 0x0 0x1a000>;
|
|
interrupt-parent = <&disp_intr>;
|
|
interrupts = <2>, <9>, <16>;
|
|
interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
|
|
};
|
|
};
|