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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1f70557790
Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall. It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
80 lines
979 B
Plaintext
80 lines
979 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
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*/
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/dts-v1/;
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#include "ax3000.dtsi"
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/ {
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model = "Axiado AX3000 EVK";
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compatible = "axiado,ax3000-evk", "axiado,ax3000";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial3 = &uart3;
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};
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chosen {
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stdout-path = "serial3:115200";
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};
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memory@0 {
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device_type = "memory";
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/* Cortex-A53 will use following memory map */
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reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
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<0x00000004 0x00000000 0x00000000 0x80000000>;
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};
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};
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/* GPIO bank 0 - 7 */
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&gpio6 {
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status = "okay";
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};
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&gpio7 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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