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04f08ef291
With the recent defining of preferred naming for fixed clock and regulator nodes, convert the Arm Ltd. boards to use the preferred names. In the cases which had a unit-address, warnings about missing "reg" property are fixed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/20240528191536.1444649-2-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240630-arm-dts-fixes-2-v1-1-a32ba57e5b1d@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
153 lines
3.3 KiB
Plaintext
153 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* LogicTile Express 20MG
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* V2F-1XV7
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*
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* Cortex-A53 (2 cores) Soft Macrocell Model
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*
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* HBI-0247C
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "arm/arm/vexpress-v2m-rs1.dtsi"
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/ {
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model = "V2F-1XV7 Cortex-A53x2 SMM";
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arm,hbi = <0x247>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = "serial0:38400n8";
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};
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 0>;
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next-level-cache = <&L2_0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 1>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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smbclk: clock-controller {
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/* SMC clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 4>;
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freq-range = <40000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "smclk";
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};
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regulator-vio {
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/* VIO to expansion board above */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VIO_UP";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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regulator-12v {
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/* 12V from power connector J6 */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 1>;
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regulator-name = "12";
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regulator-always-on;
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};
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temp-fpga {
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/* FPGA temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "FPGA";
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};
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};
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smb: bus@8000000 {
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ranges = <0x8000000 0 0x8000000 0x18000000>;
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};
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};
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