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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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34f3b3745c
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
78 lines
1.8 KiB
Plaintext
78 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*/
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/dts-v1/;
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#include "morello.dtsi"
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/ {
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model = "Arm Morello Fixed Virtual Platform";
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compatible = "arm,morello-fvp", "arm,morello";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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bp_refclock24mhz: clock-24000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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block_0: virtio_block@1c170000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c170000 0x0 0x200>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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};
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net_0: virtio_net@1c180000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c180000 0x0 0x200>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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};
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rng_0: virtio_rng@1c190000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c190000 0x0 0x200>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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};
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p9_0: virtio_p9@1c1a0000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c1a0000 0x0 0x200>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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kmi_0: kmi@1c150000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c150000 0x0 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi_1: kmi@1c160000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c160000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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eth_0: ethernet@1d100000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x1d100000 0x0 0x10000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&uart0 {
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status = "okay";
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};
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