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a3ffd38110
Add information about CPU caches in the P-cluster of Apple A10 SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan <towinchenmi@gmail.com> Link: https://lore.kernel.org/r/20250220-caches-v1-6-2c7011097768@gmail.com Signed-off-by: Sven Peter <sven@svenpeter.dev>
262 lines
6.7 KiB
Plaintext
262 lines
6.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Apple T8010 "A10" SoC
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*
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* Other names: H9P, "Cayman"
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*
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* Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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/ {
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interrupt-parent = <&aic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clkref";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "apple,hurricane-zephyr";
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reg = <0x0 0x0>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&fusion_opp>;
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performance-domains = <&cpufreq>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>; /* P-core */
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d-cache-size = <0x10000>; /* P-core */
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};
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cpu1: cpu@1 {
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compatible = "apple,hurricane-zephyr";
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reg = <0x0 0x1>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&fusion_opp>;
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performance-domains = <&cpufreq>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>; /* P-core */
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d-cache-size = <0x10000>; /* P-core */
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x300000>; /* P-cluster */
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};
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};
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fusion_opp: opp-table {
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compatible = "operating-points-v2";
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/*
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* Apple Fusion Architecture: Hardware big.LITTLE switcher
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* that use p-state transitions to switch between cores.
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* Only one type of core can be active at a given time.
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*
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* The E-core frequencies are adjusted so performance scales
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* linearly with reported clock speed.
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*/
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opp01 {
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opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
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opp-level = <1>;
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clock-latency-ns = <11000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
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opp-level = <2>;
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clock-latency-ns = <49000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
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opp-level = <3>;
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clock-latency-ns = <13000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
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opp-level = <4>;
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clock-latency-ns = <18000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <756000000>;
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opp-level = <5>;
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clock-latency-ns = <35000>;
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};
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opp06 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-level = <6>;
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clock-latency-ns = <31000>;
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};
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opp07 {
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opp-hz = /bits/ 64 <1356000000>;
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opp-level = <7>;
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clock-latency-ns = <37000>;
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};
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opp08 {
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opp-hz = /bits/ 64 <1644000000>;
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opp-level = <8>;
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clock-latency-ns = <39500>;
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};
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hurricane_opp09: opp09 {
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opp-hz = /bits/ 64 <1944000000>;
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opp-level = <9>;
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clock-latency-ns = <46000>;
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status = "disabled"; /* Not available on N112 */
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};
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hurricane_opp10: opp10 {
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opp-hz = /bits/ 64 <2244000000>;
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opp-level = <10>;
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clock-latency-ns = <56000>;
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status = "disabled"; /* Not available on N112 */
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};
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#if 0
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/* Not available until CPU deep sleep is implemented */
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hurricane_opp11: opp11 {
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opp-hz = /bits/ 64 <2340000000>;
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opp-level = <11>;
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clock-latency-ns = <56000>;
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turbo-mode;
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status = "disabled"; /* Not available on N112 */
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};
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#endif
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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nonposted-mmio;
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ranges;
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cpufreq: performance-controller@202f20000 {
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compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
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reg = <0x2 0x02f20000 0 0x1000>;
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#performance-domain-cells = <0>;
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};
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serial0: serial@20a0c0000 {
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compatible = "apple,s5l-uart";
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reg = <0x2 0x0a0c0000 0x0 0x4000>;
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reg-io-width = <4>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>;
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/* Use the bootloader-enabled clocks for now. */
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clocks = <&clkref>, <&clkref>;
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clock-names = "uart", "clk_uart_baud0";
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power-domains = <&ps_uart0>;
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status = "disabled";
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};
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pmgr: power-management@20e000000 {
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compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0xe000000 0 0x8c000>;
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};
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aic: interrupt-controller@20e100000 {
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compatible = "apple,t8010-aic", "apple,aic";
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reg = <0x2 0x0e100000 0x0 0x100000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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power-domains = <&ps_aic>;
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};
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dwi_bl: backlight@20e200080 {
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compatible = "apple,t8010-dwi-bl", "apple,dwi-bl";
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reg = <0x2 0x0e200080 0x0 0x8>;
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power-domains = <&ps_dwi>;
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status = "disabled";
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};
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pinctrl_ap: pinctrl@20f100000 {
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compatible = "apple,t8010-pinctrl", "apple,pinctrl";
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reg = <0x2 0x0f100000 0x0 0x100000>;
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power-domains = <&ps_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_ap 0 0 208>;
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apple,npins = <208>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_aop: pinctrl@2100f0000 {
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compatible = "apple,t8010-pinctrl", "apple,pinctrl";
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reg = <0x2 0x100f0000 0x0 0x100000>;
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power-domains = <&ps_aop_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aop 0 0 42>;
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apple,npins = <42>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmgr_mini: power-management@210200000 {
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compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x10200000 0 0x84000>;
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};
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wdt: watchdog@2102b0000 {
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compatible = "apple,t8010-wdt", "apple,wdt";
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reg = <0x2 0x102b0000 0x0 0x4000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&aic>;
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interrupt-names = "phys", "virt";
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/* Note that A10 doesn't actually have a hypervisor (EL2 is not implemented). */
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interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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#include "t8010-pmgr.dtsi"
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