mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 15:14:52 +00:00
ac75da105e
Only one fix: Correct the name of the A523's EMAC0 to GMAC0, as seen in the SoC's datasheets. The matching DT binding change is in the net tree. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmh2iT4OHHdlbnNAY3Np ZS5vcmcACgkQOJpUIZwPJDCMJBAAuauzK0XFSSwuzxlkd2b4fb9iY8V8U+h4T6E0 T83snFr3IDZxRU3z9+6EKhIAyh/yHpu8wv27jMNyb6UAbafzhqYaCENXdIrI7lDX CzgDCJJWPTJ9L/Iq5EY+BXSBNaHQz1PLrryjdLJeNSzxXWP4k62oPCE09HioYIvK hMEUIyH9jdTK6h4jfp0J0YHYfDZPr4ix33Ua33ToPnTYeaMeowaWDZ2I/IXyhmG7 q+XRzdNrpcMuKQH5hpSTDYI1TjonWa1jovpYH9uktuzb7CHHz2C9f3wxz9X2xpui nxa44UoqKF0XfP3Luur9cfXHS6zq5HqKRaXkCP9EiXoIpocjo5rCHqvIabyC+6QU ACRrbp/9rCJ/XZm5MRvXD3+JlcF+SFJ3vYhZgk1iLXFFEPGgfUezf0s6hAUv5xGc OnxmF2ztxxXVAKCkRFG7JVbyHzQmKojX9lZUVWQP1dRZCfaQ1dqAN6oCO1NuVvLc mPVgftt3N2XDaM/XCp054RFBu0Dmjm6oIUNJy2Jc59ED5FF+Erit+xTqYfv9iZGu PfyBk43lPhFr+6twsYsaivoh45px7aCRAuKnwY4AizIjr01ZeVjc1snauiUS7pzo jtdIESYuaRnmTE1tiY0keAB5y4OH/jxB61jJ4IwIUIEGzySrmG8HchizVnd0UYoA eJsh/Jw= =j8oj -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiEp40ACgkQmmx57+YA GNnQ9w//YpHI9/IqYMspsOk+ML2JLsRlbYWzmrZPAnWdQtFQ+sthqkr6bSA5zohn DQp04yGB5YPHD/R6n4Us2K0tb/UFQLQl2s9Owg0xZkoAdqwoRTBKP2nnYh5mtoK8 pf7KgfiMWi29rqNZmEPbk9onrhXIhAaLNJomIbDBaY3rsMxNnuEdDN+KO6mwTcrf RtBJqQKNeVbVniqmVn7o3IJiN5hLPKPrZ9r2FkX+K/0GHh4PPkQNyUJHLhvdsady 1EFPUqTqTp9ykPMj5KZ1TBs05dEBexMYPeGfZdTbLN6sXJQrAy9JN5XrSg6QffX0 NbzeO8r0YnwA2bsFnoF7xIUCdGvuI2jc4bvtVPt2wPrjINmSA83RJstJZcm1r/Uh qIFGYqgUJotqRzEJkOTvce32OG9T/Q7DcbC0uFenXjMdLU9hV6MDEFpPj2t875xr Y6P4dzp4TcR/28OA/nrmYhOV6Y7LOVzW7Y2D23iYltA62/GPR/dzlthw+nzYLecu 6/T4sH/LtACHmZNbbdAtf07rZmMYg1K16HJLcHxm5egp27AxIqujsy+kFVdtASXn Fc43ISthJVmdCVg7LHhVr5NrkKbgk4GZgZ5uL94+mYxZBMyMEdUP9Jqn/BjMaXt6 WPzkP/PZNEAlogAS6LSumMJvCcmrJdbCGplMWkUliMAgjbpL2e0= =xPoN -----END PGP SIGNATURE----- Merge tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt Allwinner fixes for 6.16 Only one fix: Correct the name of the A523's EMAC0 to GMAC0, as seen in the SoC's datasheets. The matching DT binding change is in the net tree. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
695 lines
17 KiB
Plaintext
695 lines
17 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
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// Copyright (C) 2023-2024 Arm Ltd.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/clock/sun55i-a523-ccu.h>
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#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
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#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h>
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#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x000>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@400 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x400>;
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enable-method = "psci";
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};
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cpu5: cpu@500 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x500>;
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enable-method = "psci";
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};
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cpu6: cpu@600 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x600>;
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enable-method = "psci";
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};
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cpu7: cpu@700 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x700>;
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enable-method = "psci";
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};
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};
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osc24M: osc24M-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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gpu: gpu@1800000 {
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compatible = "allwinner,sun55i-a523-mali",
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"arm,mali-valhall-jm";
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reg = <0x1800000 0x10000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "job", "mmu", "gpu";
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clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
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clock-names = "core", "bus";
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power-domains = <&pck600 PD_GPU>;
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resets = <&ccu RST_BUS_GPU>;
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status = "disabled";
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};
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pio: pinctrl@2000000 {
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compatible = "allwinner,sun55i-a523-pinctrl";
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reg = <0x2000000 0x800>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mmc0_pins: mmc0-pins {
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pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5";
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allwinner,pinmux = <2>;
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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/omit-if-no-ref/
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mmc1_pins: mmc1-pins {
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pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5";
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allwinner,pinmux = <2>;
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC0", "PC1" ,"PC5", "PC6", "PC8",
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"PC9", "PC10", "PC11", "PC13", "PC14",
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"PC15", "PC16";
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allwinner,pinmux = <3>;
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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rgmii0_pins: rgmii0-pins {
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pins = "PH0", "PH1", "PH2", "PH3", "PH4",
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"PH5", "PH6", "PH7", "PH9", "PH10",
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"PH14", "PH15", "PH16", "PH17", "PH18";
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allwinner,pinmux = <5>;
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function = "gmac0";
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drive-strength = <40>;
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bias-disable;
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};
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB9", "PB10";
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allwinner,pinmux = <2>;
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function = "uart0";
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};
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/omit-if-no-ref/
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uart1_pins: uart1-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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allwinner,pinmux = <2>;
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};
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/omit-if-no-ref/
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uart1_rts_cts_pins: uart1-rts-cts-pins {
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pins = "PG8", "PG9";
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function = "uart1";
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allwinner,pinmux = <2>;
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};
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};
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ccu: clock-controller@2001000 {
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compatible = "allwinner,sun55i-a523-ccu";
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reg = <0x02001000 0x1000>;
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clocks = <&osc24M>, <&rtc CLK_OSC32K>,
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<&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>;
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clock-names = "hosc", "losc",
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"iosc", "losc-fanout";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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wdt: watchdog@2050000 {
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compatible = "allwinner,sun55i-a523-wdt";
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reg = <0x2050000 0x20>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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status = "okay";
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};
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uart0: serial@2500000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02500000 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@2500400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02500400 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@2500800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02500800 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@2500c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02500c00 0x400>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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uart4: serial@2501000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02501000 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART4>;
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resets = <&ccu RST_BUS_UART4>;
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status = "disabled";
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};
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uart5: serial@2501400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02501400 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART5>;
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resets = <&ccu RST_BUS_UART5>;
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status = "disabled";
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};
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uart6: serial@2501800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02501800 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART6>;
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resets = <&ccu RST_BUS_UART6>;
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status = "disabled";
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};
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uart7: serial@2501c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x02501c00 0x400>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART7>;
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resets = <&ccu RST_BUS_UART7>;
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status = "disabled";
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};
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i2c0: i2c@2502000 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502000 0x400>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@2502400 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502400 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@2502800 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502800 0x400>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c3: i2c@2502c00 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502c00 0x400>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C3>;
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resets = <&ccu RST_BUS_I2C3>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c4: i2c@2503000 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2503000 0x400>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C4>;
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resets = <&ccu RST_BUS_I2C4>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c5: i2c@2503400 {
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compatible = "allwinner,sun55i-a523-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2503400 0x400>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C5>;
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resets = <&ccu RST_BUS_I2C5>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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|
syscon: syscon@3000000 {
|
|
compatible = "allwinner,sun55i-a523-system-control",
|
|
"allwinner,sun50i-a64-system-control";
|
|
reg = <0x03000000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
};
|
|
|
|
sid: efuse@3006000 {
|
|
compatible = "allwinner,sun55i-a523-sid",
|
|
"allwinner,sun50i-a64-sid";
|
|
reg = <0x03006000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@3400000 {
|
|
compatible = "arm,gic-v3";
|
|
#address-cells = <1>;
|
|
#interrupt-cells = <3>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
interrupt-controller;
|
|
reg = <0x3400000 0x10000>,
|
|
<0x3460000 0x100000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-noncoherent;
|
|
|
|
its: msi-controller@3440000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0x3440000 0x20000>;
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
dma-noncoherent;
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@4020000 {
|
|
compatible = "allwinner,sun55i-a523-mmc",
|
|
"allwinner,sun20i-d1-mmc";
|
|
reg = <0x04020000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC0>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc0_pins>;
|
|
status = "disabled";
|
|
|
|
max-frequency = <150000000>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
cap-sdio-irq;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@4021000 {
|
|
compatible = "allwinner,sun55i-a523-mmc",
|
|
"allwinner,sun20i-d1-mmc";
|
|
reg = <0x04021000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC1>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
status = "disabled";
|
|
|
|
max-frequency = <150000000>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
cap-sdio-irq;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@4022000 {
|
|
compatible = "allwinner,sun55i-a523-mmc",
|
|
"allwinner,sun20i-d1-mmc";
|
|
reg = <0x04022000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC2>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins>;
|
|
status = "disabled";
|
|
|
|
max-frequency = <150000000>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
cap-sdio-irq;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usb_otg: usb@4100000 {
|
|
compatible = "allwinner,sun55i-a523-musb",
|
|
"allwinner,sun8i-a33-musb";
|
|
reg = <0x4100000 0x400>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
clocks = <&ccu CLK_BUS_OTG>;
|
|
resets = <&ccu RST_BUS_OTG>;
|
|
extcon = <&usbphy 0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@4100400 {
|
|
compatible = "allwinner,sun55i-a523-usb-phy",
|
|
"allwinner,sun20i-d1-usb-phy";
|
|
reg = <0x4100400 0x100>,
|
|
<0x4101800 0x100>,
|
|
<0x4200800 0x100>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu0",
|
|
"pmu1";
|
|
clocks = <&osc24M>,
|
|
<&osc24M>;
|
|
clock-names = "usb0_phy",
|
|
"usb1_phy";
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
<&ccu RST_USB_PHY1>;
|
|
reset-names = "usb0_reset",
|
|
"usb1_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
ehci0: usb@4101000 {
|
|
compatible = "allwinner,sun55i-a523-ehci",
|
|
"generic-ehci";
|
|
reg = <0x4101000 0x100>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_BUS_EHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>,
|
|
<&ccu RST_BUS_EHCI0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@4101400 {
|
|
compatible = "allwinner,sun55i-a523-ohci",
|
|
"generic-ohci";
|
|
reg = <0x4101400 0x100>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@4200000 {
|
|
compatible = "allwinner,sun55i-a523-ehci",
|
|
"generic-ehci";
|
|
reg = <0x4200000 0x100>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
<&ccu CLK_BUS_EHCI1>,
|
|
<&ccu CLK_USB_OHCI1>;
|
|
resets = <&ccu RST_BUS_OHCI1>,
|
|
<&ccu RST_BUS_EHCI1>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@4200400 {
|
|
compatible = "allwinner,sun55i-a523-ohci",
|
|
"generic-ohci";
|
|
reg = <0x4200400 0x100>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
<&ccu CLK_USB_OHCI1>;
|
|
resets = <&ccu RST_BUS_OHCI1>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@4500000 {
|
|
compatible = "allwinner,sun55i-a523-gmac0",
|
|
"allwinner,sun50i-a64-emac";
|
|
reg = <0x04500000 0x10000>;
|
|
clocks = <&ccu CLK_BUS_EMAC0>;
|
|
clock-names = "stmmaceth";
|
|
resets = <&ccu RST_BUS_EMAC0>;
|
|
reset-names = "stmmaceth";
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&rgmii0_pins>;
|
|
syscon = <&syscon>;
|
|
status = "disabled";
|
|
|
|
mdio0: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
ppu: power-controller@7001400 {
|
|
compatible = "allwinner,sun55i-a523-ppu";
|
|
reg = <0x07001400 0x400>;
|
|
clocks = <&r_ccu CLK_BUS_R_PPU1>;
|
|
resets = <&r_ccu RST_BUS_R_PPU1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
r_ccu: clock-controller@7010000 {
|
|
compatible = "allwinner,sun55i-a523-r-ccu";
|
|
reg = <0x7010000 0x250>;
|
|
clocks = <&osc24M>,
|
|
<&rtc CLK_OSC32K>,
|
|
<&rtc CLK_IOSC>,
|
|
<&ccu CLK_PLL_PERIPH0_200M>,
|
|
<&ccu CLK_PLL_AUDIO0_4X>;
|
|
clock-names = "hosc",
|
|
"losc",
|
|
"iosc",
|
|
"pll-periph",
|
|
"pll-audio";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
nmi_intc: interrupt-controller@7010320 {
|
|
compatible = "allwinner,sun55i-a523-nmi";
|
|
reg = <0x07010320 0xc>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_pio: pinctrl@7022000 {
|
|
compatible = "allwinner,sun55i-a523-r-pinctrl";
|
|
reg = <0x7022000 0x800>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB0>,
|
|
<&osc24M>,
|
|
<&rtc CLK_OSC32K>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
r_i2c_pins: r-i2c-pins {
|
|
pins = "PL0" ,"PL1";
|
|
allwinner,pinmux = <2>;
|
|
function = "r_i2c0";
|
|
};
|
|
};
|
|
|
|
pck600: power-controller@7060000 {
|
|
compatible = "allwinner,sun55i-a523-pck-600";
|
|
reg = <0x07060000 0x8000>;
|
|
clocks = <&r_ccu CLK_BUS_R_PPU0>;
|
|
resets = <&r_ccu RST_BUS_R_PPU0>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
r_i2c0: i2c@7081400 {
|
|
compatible = "allwinner,sun55i-a523-i2c",
|
|
"allwinner,sun8i-v536-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x07081400 0x400>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_BUS_R_I2C0>;
|
|
resets = <&r_ccu RST_BUS_R_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_i2c_pins>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
rtc: rtc@7090000 {
|
|
compatible = "allwinner,sun55i-a523-rtc",
|
|
"allwinner,sun50i-r329-rtc";
|
|
reg = <0x7090000 0x400>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_BUS_R_RTC>,
|
|
<&osc24M>,
|
|
<&r_ccu CLK_R_AHB>;
|
|
clock-names = "bus", "hosc", "ahb";
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
};
|