mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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d172b9237e
Introduce ethernet controller nodes to EN7581 SoC and EN7581 evaluation board. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20250520-en7581-net-v1-1-5317f8e829ad@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
400 lines
8.6 KiB
Plaintext
400 lines
8.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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npu-binary@84000000 {
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no-map;
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reg = <0x0 0x84000000 0x0 0xa00000>;
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};
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npu-flag@84b0000 {
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no-map;
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reg = <0x0 0x84b00000 0x0 0x100000>;
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};
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npu-pkt@85000000 {
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no-map;
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reg = <0x0 0x85000000 0x0 0x1a00000>;
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};
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npu-phyaddr@86b00000 {
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no-map;
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reg = <0x0 0x86b00000 0x0 0x100000>;
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};
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npu-rxdesc@86d00000 {
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no-map;
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reg = <0x0 0x86d00000 0x0 0x100000>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-level = <2>;
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cache-unified;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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clk20m: clock-20000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@9000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x09000000 0x0 0x20000>,
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<0x0 0x09080000 0x0 0x80000>,
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<0x0 0x09400000 0x0 0x2000>,
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<0x0 0x09500000 0x0 0x2000>,
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<0x0 0x09600000 0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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spi@1fa10000 {
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compatible = "airoha,en7581-snand";
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reg = <0x0 0x1fa10000 0x0 0x140>,
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<0x0 0x1fa11000 0x0 0x160>;
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clocks = <&scuclk EN7523_CLK_SPI>;
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clock-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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spi_nand: nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <2>;
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};
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};
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scuclk: clock-controller@1fb00000 {
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compatible = "airoha,en7581-scu";
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reg = <0x0 0x1fb00000 0x0 0x970>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pbus_csr: syscon@1fbe3400 {
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compatible = "airoha,en7581-pbus-csr", "syscon";
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reg = <0x0 0x1fbe3400 0x0 0xff>;
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};
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pciephy: phy@1fa5a000 {
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compatible = "airoha,en7581-pcie-phy";
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reg = <0x0 0x1fa5a000 0x0 0xfff>,
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<0x0 0x1fa5b000 0x0 0xfff>,
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<0x0 0x1fa5c000 0x0 0xfff>,
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<0x0 0x1fc10044 0x0 0x4>,
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<0x0 0x1fc30044 0x0 0x4>,
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<0x0 0x1fc15030 0x0 0x104>;
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reg-names = "csr-2l", "pma0", "pma1",
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"p0-xr-dtime", "p1-xr-dtime",
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"rx-aeq";
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#phy-cells = <0>;
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};
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pcie0: pcie@1fc00000 {
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compatible = "airoha,en7581-pcie";
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device_type = "pci";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x1fc00000 0x0 0x1670>;
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reg-names = "pcie-mac";
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clocks = <&scuclk EN7523_CLK_PCIE>;
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clock-names = "sys-ck";
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phys = <&pciephy>;
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phy-names = "pcie-phy";
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ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
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resets = <&scuclk EN7581_PCIE0_RST>,
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<&scuclk EN7581_PCIE1_RST>,
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<&scuclk EN7581_PCIE2_RST>;
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reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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status = "disabled";
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1fc20000 {
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compatible = "airoha,en7581-pcie";
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device_type = "pci";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x1fc20000 0x0 0x1670>;
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reg-names = "pcie-mac";
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clocks = <&scuclk EN7523_CLK_PCIE>;
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clock-names = "sys-ck";
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phys = <&pciephy>;
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phy-names = "pcie-phy";
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ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
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resets = <&scuclk EN7581_PCIE0_RST>,
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<&scuclk EN7581_PCIE1_RST>,
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<&scuclk EN7581_PCIE2_RST>;
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reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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status = "disabled";
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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uart1: serial@1fbf0000 {
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compatible = "ns16550";
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reg = <0x0 0x1fbf0000 0x0 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1843200>;
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};
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rng@1faa1000 {
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compatible = "airoha,en7581-trng";
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reg = <0x0 0x1faa1000 0x0 0xc04>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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};
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system-controller@1fbf0200 {
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compatible = "airoha,en7581-gpio-sysctl", "syscon",
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"simple-mfd";
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reg = <0x0 0x1fbf0200 0x0 0xc0>;
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en7581_pinctrl: pinctrl {
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compatible = "airoha,en7581-pinctrl";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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i2c0: i2c@1fbf8000 {
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compatible = "mediatek,mt7621-i2c";
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reg = <0x0 0x1fbf8000 0x0 0x100>;
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resets = <&scuclk EN7581_I2C2_RST>;
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clocks = <&clk20m>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@1fbf8100 {
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compatible = "mediatek,mt7621-i2c";
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reg = <0x0 0x1fbf8100 0x0 0x100>;
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resets = <&scuclk EN7581_I2C_MASTER_RST>;
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clocks = <&clk20m>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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eth: ethernet@1fb50000 {
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compatible = "airoha,en7581-eth";
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reg = <0 0x1fb50000 0 0x2600>,
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<0 0x1fb54000 0 0x2000>,
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<0 0x1fb56000 0 0x2000>;
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reg-names = "fe", "qdma0", "qdma1";
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resets = <&scuclk EN7581_FE_RST>,
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<&scuclk EN7581_FE_PDMA_RST>,
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<&scuclk EN7581_FE_QDMA_RST>,
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<&scuclk EN7581_XSI_MAC_RST>,
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<&scuclk EN7581_DUAL_HSI0_MAC_RST>,
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<&scuclk EN7581_DUAL_HSI1_MAC_RST>,
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<&scuclk EN7581_HSI_MAC_RST>,
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<&scuclk EN7581_XFP_MAC_RST>;
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reset-names = "fe", "pdma", "qdma",
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"xsi-mac", "hsi0-mac", "hsi1-mac",
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"hsi-mac", "xfp-mac";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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gdm1: ethernet@1 {
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compatible = "airoha,eth-mac";
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reg = <1>;
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phy-mode = "internal";
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status = "disabled";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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