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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
6469b2fead
Fix "thermal_sys: cpu_thermal: Failed to read thermal-sensors cells: -2" error on boot for omap3/4. This is caused by wrong addressing in the dts for bandgap sensor for single sensor instances. Note that omap4-cpu-thermal.dtsi is shared across omap4/5 and dra7, so we can't just change the addressing in omap4-cpu-thermal.dtsi. Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: Carl Philipp Klemm <philipp@uvos.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Fixes:a761d517bb("ARM: dts: omap3: Add cpu_thermal zone") Fixes:0bbf6c54d1("arm: dts: add omap4 CPU thermal data") Signed-off-by: Tony Lindgren <tony@atomide.com>
129 lines
3.3 KiB
Plaintext
129 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP4460 SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "omap4.dtsi"
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/ {
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cpus {
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/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
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cpu0: cpu@0 {
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operating-points = <
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/* kHz uV */
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350000 1025000
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700000 1200000
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920000 1313000
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>;
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clock-latency = <300000>; /* From legacy driver */
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/* cooling options */
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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thermal-zones {
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#include "omap4-cpu-thermal.dtsi"
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};
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ocp {
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bandgap: bandgap@4a002260 {
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reg = <0x4a002260 0x4
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0x4a00232C 0x4
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0x4a002378 0x18>;
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compatible = "ti,omap4460-bandgap";
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interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
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gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
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#thermal-sensor-cells = <0>;
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};
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abb_mpu: regulator-abb-mpu {
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status = "okay";
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reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
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<0x4A002268 0x4>;
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reg-names = "base-address", "int-address",
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"efuse-address";
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1025000 0 0 0 0 0
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1200000 0 0 0 0 0
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1313000 0 0 0x100000 0x40000 0
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1375000 1 0 0 0 0
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1389000 1 0 0 0 0
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>;
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};
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abb_iva: regulator-abb-iva {
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status = "okay";
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reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
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<0x4A002268 0x4>;
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reg-names = "base-address", "int-address",
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"efuse-address";
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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950000 0 0 0 0 0
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1140000 0 0 0 0 0
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1291000 0 0 0x200000 0 0
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1375000 1 0 0 0 0
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1376000 1 0 0 0 0
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>;
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};
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};
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};
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&cpu_thermal {
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thermal-sensors = <&bandgap>;
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coefficients = <348 (-9301)>;
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};
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/* Only some L4 CFG interconnect ranges are different on 4460 */
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&l4_cfg_segment_300000 {
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ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
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<0x00040000 0x00340000 0x001000>, /* ap 68 */
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<0x00020000 0x00320000 0x004000>, /* ap 71 */
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<0x00024000 0x00324000 0x002000>, /* ap 72 */
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<0x00026000 0x00326000 0x001000>, /* ap 73 */
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<0x00027000 0x00327000 0x001000>, /* ap 74 */
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<0x00028000 0x00328000 0x001000>, /* ap 75 */
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<0x00029000 0x00329000 0x001000>, /* ap 76 */
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<0x00030000 0x00330000 0x010000>, /* ap 77 */
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<0x0002a000 0x0032a000 0x002000>, /* ap 90 */
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<0x0002c000 0x0032c000 0x004000>, /* ap 91 */
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<0x00010000 0x00310000 0x008000>, /* ap 92 */
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<0x00018000 0x00318000 0x004000>, /* ap 93 */
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<0x0001c000 0x0031c000 0x002000>, /* ap 94 */
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<0x0001e000 0x0031e000 0x002000>; /* ap 95 */
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};
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&l4_cfg_target_0 {
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ranges = <0x00000000 0x00000000 0x00010000>,
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<0x00010000 0x00010000 0x00008000>,
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<0x00018000 0x00018000 0x00004000>,
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<0x0001c000 0x0001c000 0x00002000>,
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<0x0001e000 0x0001e000 0x00002000>,
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<0x00020000 0x00020000 0x00004000>,
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<0x00024000 0x00024000 0x00002000>,
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<0x00026000 0x00026000 0x00001000>,
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<0x00027000 0x00027000 0x00001000>,
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<0x00028000 0x00028000 0x00001000>,
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<0x00029000 0x00029000 0x00001000>,
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<0x0002a000 0x0002a000 0x00002000>,
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<0x0002c000 0x0002c000 0x00004000>,
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<0x00030000 0x00030000 0x00010000>;
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};
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&pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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};
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/include/ "omap446x-clocks.dtsi"
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