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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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96a64e9730
Operating stable without reduced chip life at 1Ghz needs several technologies working: The technologies involve - SmartReflex - DVFS As this cannot directly specified in the OPP table as dependecies in the devicetree yet, use the turbo flag again to mark this OPP as something special to have some kind of opt-in. So revert commit5f1bf7ae84("ARM: dts: omap36xx: Remove turbo mode for 1GHz variants") Practical reasoning: At least the GTA04A5 (DM3730) has become unstable with that OPP enabled. Furthermore nothing enforces the availability of said technologies, even in the kernel configuration, so allow users to rather opt-in. Cc: Stable@vger.kernel.org Fixes:5f1bf7ae84("ARM: dts: omap36xx: Remove turbo mode for 1GHz variants") Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20241018214727.275162-1-andreas@kemnade.info Signed-off-by: Kevin Hilman <khilman@baylibre.com>
257 lines
6.0 KiB
Plaintext
257 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP3 SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/media/omap3-isp.h>
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#include "omap3.dtsi"
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/ {
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aliases {
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serial3 = &uart4;
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};
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cpus {
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/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
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cpu: cpu@0 {
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operating-points-v2 = <&cpu0_opp_table>;
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vbb-supply = <&abb_mpu_iva>;
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clock-latency = <300000>; /* From omap-cpufreq driver */
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#cooling-cells = <2>;
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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opp-50-300000000 {
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/* OPP50 */
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opp-hz = /bits/ 64 <300000000>;
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/*
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* we currently only select the max voltage from table
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* Table 4-19 of the DM3730 Data sheet (SPRS685B)
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* Format is: cpu0-supply: <target min max>
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* vbb-supply: <target min max>
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*/
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opp-microvolt = <1012500 1012500 1012500>,
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<1012500 1012500 1012500>;
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/*
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* first value is silicon revision bit mask
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* second one is "speed binned" bit mask
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*/
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opp-supported-hw = <0xffffffff 3>;
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opp-suspend;
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};
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opp-100-600000000 {
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/* OPP100 */
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1200000 1200000 1200000>,
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<1200000 1200000 1200000>;
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opp-supported-hw = <0xffffffff 3>;
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};
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opp-130-800000000 {
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/* OPP130 */
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1325000 1325000 1325000>,
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<1325000 1325000 1325000>;
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opp-supported-hw = <0xffffffff 3>;
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};
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opp-1000000000 {
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/* OPP1G */
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1375000 1375000 1375000>,
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<1375000 1375000 1375000>;
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/* only on am/dm37x with speed-binned bit set */
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opp-supported-hw = <0xffffffff 2>;
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turbo-mode;
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};
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};
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opp_supply_mpu_iva: opp-supply {
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compatible = "ti,omap-opp-supply";
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ti,absolute-max-voltage-uv = <1375000>;
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};
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ocp@68000000 {
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uart4: serial@49042000 {
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compatible = "ti,omap3-uart";
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reg = <0x49042000 0x400>;
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interrupts = <80>;
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dmas = <&sdma 81 &sdma 82>;
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dma-names = "tx", "rx";
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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};
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abb_mpu_iva: regulator-abb-mpu {
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compatible = "ti,abb-v1";
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regulator-name = "abb_mpu_iva";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <0x483072f0 0x8>, <0x48306818 0x4>;
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reg-names = "base-address", "int-address";
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ti,tranxdone-status-mask = <0x4000000>;
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clocks = <&sys_ck>;
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ti,settling-time = <30>;
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ti,clock-cycles = <8>;
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1012500 0 0 0 0 0
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1200000 0 0 0 0 0
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1325000 0 0 0 0 0
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1375000 1 0 0 0 0
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>;
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};
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omap3_pmx_core2: pinmux@480025a0 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025a0 0x5c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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isp: isp@480bc000 {
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compatible = "ti,omap3-isp";
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reg = <0x480bc000 0x12fc
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0x480bd800 0x0600>;
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interrupts = <24>;
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iommus = <&mmu_isp>;
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syscon = <&scm_conf 0x2f0>;
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ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
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#clock-cells = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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bandgap: bandgap@48002524 {
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reg = <0x48002524 0x4>;
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compatible = "ti,omap36xx-bandgap";
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#thermal-sensor-cells = <0>;
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};
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target-module@480cb000 {
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compatible = "ti,sysc-omap3630-sr", "ti,sysc";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sr2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480cb000 0x001000>;
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smartreflex_core: smartreflex@0 {
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compatible = "ti,omap3-smartreflex-core";
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reg = <0 0x400>;
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interrupts = <19>;
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};
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};
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target-module@480c9000 {
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compatible = "ti,sysc-omap3630-sr", "ti,sysc";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sr1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480c9000 0x001000>;
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-mpu-iva";
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reg = <0 0x400>;
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interrupts = <18>;
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};
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};
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/*
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* Note that the sysconfig register layout is a subset of the
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* "ti,sysc-omap4" type register with just sidle and midle bits
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* available while omap34xx has "ti,sysc-omap2" type sysconfig.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5000fe00 0x4>,
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<0x5000fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x2000000>;
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gpu@0 {
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compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
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reg = <0x0 0x2000000>; /* 32MB */
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interrupts = <21>;
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};
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};
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};
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thermal_zones: thermal-zones {
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#include "omap3-cpu-thermal.dtsi"
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};
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};
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&sdma {
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compatible = "ti,omap3630-sdma", "ti,omap-sdma";
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};
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/* OMAP3630 needs dss_96m_fck for VENC */
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&venc {
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clocks = <&dss_tv_fck>, <&dss_96m_fck>;
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clock-names = "fck", "tv_dac_clk";
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};
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&ssi {
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status = "okay";
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clocks = <&ssi_ssr_fck>,
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<&ssi_sst_fck>,
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<&ssi_ick>;
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clock-names = "ssi_ssr_fck",
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"ssi_sst_fck",
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"ssi_ick";
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};
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&usb_otg_target {
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clocks = <&hsotgusb_ick_3430es2>;
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};
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/include/ "omap34xx-omap36xx-clocks.dtsi"
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/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
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/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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/include/ "omap36xx-clocks.dtsi"
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