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linux-loongson/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts
Rob Herring 724ba67515 ARM: dts: Move .dts files to vendor sub-directories 
The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-21 11:39:50 -06:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2020 Protonic Holland
* Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx6ull.dtsi"
/ {
model = "JOZ Access Point";
compatible = "joz,jozacp", "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
/* On board name LED_RGB1 */
led-controller-1 {
compatible = "pwm-leds";
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
pwms = <&pwm1 0 10000000 0>;
max-brightness = <255>;
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
pwms = <&pwm3 0 10000000 0>;
max-brightness = <255>;
};
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
pwms = <&pwm5 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
/* On board name LED_RGB2 */
led-controller-2 {
compatible = "pwm-leds";
led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
pwms = <&pwm2 0 10000000 0>;
max-brightness = <255>;
};
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <4>;
pwms = <&pwm4 0 10000000 0>;
max-brightness = <255>;
};
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <5>;
pwms = <&pwm6 0 10000000 0>;
max-brightness = <255>;
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_5v0>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vbus: regulator-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vbus>;
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_5v0>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&cpu0 {
clock-frequency = <792000000>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
status = "okay";
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
vbus-supply = <&reg_vbus>;
dr_mode = "host";
over-current-active-low;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
vmmc-supply = <&reg_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
cap-mmc-hw-reset;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sd;
non-removable;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_can1: can1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* HW Revision */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
/* HW ID */
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
/* Digital inputs */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000
/* Isolated outputs */
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020
MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010
>;
};
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010
>;
};
pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0
MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_vbus: vbus0grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0
>;
};
pinctrl_wifi_npd: wifigrp {
fsl,pins = <
/* WL_REG_ON */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020
>;
};
};
&iomuxc_snvs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_hog>;
pinctrl_snvs_hog: snvs-hog-grp {
fsl,pins = <
/* Digital outputs */
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020
/* Digital outputs fault feedback */
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000
>;
};
};
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