mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
a8281618e8
Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
96 lines
2.3 KiB
Plaintext
96 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
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* Copyright (C) 2025 Engicam srl
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*/
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/dts-v1/;
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#include "imx6ull.dtsi"
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/ {
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compatible = "engicam,microgea-imx6ull", "fsl,imx6ull";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_phy_reset>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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local-mac-address = [00 00 00 00 00 00];
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <4000>;
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reset-deassert-us = <4000>;
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};
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};
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};
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/* NAND */
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <0>;
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nand-ecc-step-size = <0>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
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>;
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};
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};
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&iomuxc_snvs {
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pinctrl_phy_reset: phy-resetgrp {
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fsl,pins = <
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MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
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>;
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};
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};
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