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linux-loongson/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts
Rob Herring 724ba67515 ARM: dts: Move .dts files to vendor sub-directories 
The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-21 11:39:50 -06:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2016 Protonic Holland
* Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Protonic PRTI6G Board";
compatible = "prt,prti6g", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
clock_ksz8081_in: clock-ksz8081-in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clock_ksz8081_out: clock-ksz8081-out {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet1_ref_pad";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
label = "debug0";
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_3v2: regulator-3v2 {
compatible = "regulator-fixed";
regulator-name = "3v2";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&clks {
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad";
assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>;
assigned-clock-parents = <&clock_ksz8081_out>;
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth1>;
phy-mode = "rmii";
phy-handle = <&rmii_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Microchip KSZ8081RNA PHY */
rmii_phy: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
clocks = <&clock_ksz8081_in>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
/* additional i2c devices are added automatically by the boot loader */
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
ti,gain = <3>;
ti,datarate = <3>;
};
channel@5 {
reg = <5>;
ti,gain = <3>;
ti,datarate = <3>;
};
channel@6 {
reg = <6>;
ti,gain = <3>;
ti,datarate = <3>;
};
channel@7 {
reg = <7>;
ti,gain = <3>;
ti,datarate = <3>;
};
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
temperature-sensor@70 {
compatible = "ti,tmp103";
reg = <0x70>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
dr_mode = "host";
over-current-active-low;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3v2>;
no-1-8-v;
disable-wp;
cap-sd-highspeed;
no-mmc;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_can1: can1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
/* SR */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
/* TERM */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
/* nSMBALERT */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
/* SR */
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0
>;
};
pinctrl_eth1: eth1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000
/* PHY ENET1_RST */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880
/* PHY ENET1_IRQ */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* HW revision detect */
/* REV_ID0 */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
/* REV_ID1 */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0
/* REV_ID2 */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
/* REV_ID3 */
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0
/* BOARD_ID0 */
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0
/* BOARD_ID1 */
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
/* BOARD_ID2 */
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
/* BOARD_ID3 */
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
/* Safety controller IO */
/* WAKE_SC */
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0
/* PROGRAM_SC */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
/* SD1 CD */
MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
>;
};
};
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