mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 22:23:05 +00:00
724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
454 lines
13 KiB
Plaintext
454 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* Contains definitions specific to the Armada XP MV78460 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-xp.dtsi"
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/ {
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model = "Marvell Armada XP MV78460 SoC";
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compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-xp-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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clock-latency = <1000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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clock-latency = <1000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <2>;
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clocks = <&cpuclk 2>;
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clock-latency = <1000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <3>;
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clocks = <&cpuclk 3>;
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clock-latency = <1000000>;
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};
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};
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soc {
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/*
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* MV78460 has 4 PCIe units Gen2.0: Two units can be
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* configured as x4 or quad x1 lanes. Two units are
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* x4/x1.
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*/
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pciec: pcie@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
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0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
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0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
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0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
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0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
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0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
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0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
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0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
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0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
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0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
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pcie1: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 58>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 0>,
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<0 0 0 2 &pcie1_intc 1>,
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<0 0 0 3 &pcie1_intc 2>,
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<0 0 0 4 &pcie1_intc 3>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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pcie1_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie2: pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 59>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2_intc 0>,
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<0 0 0 2 &pcie2_intc 1>,
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<0 0 0 3 &pcie2_intc 2>,
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<0 0 0 4 &pcie2_intc 3>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 6>;
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status = "disabled";
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pcie2_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie3: pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 60>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3_intc 0>,
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<0 0 0 2 &pcie3_intc 1>,
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<0 0 0 3 &pcie3_intc 2>,
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<0 0 0 4 &pcie3_intc 3>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 7>;
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status = "disabled";
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pcie3_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie4: pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 61>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie4_intc 0>,
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<0 0 0 2 &pcie4_intc 1>,
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<0 0 0 3 &pcie4_intc 2>,
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<0 0 0 4 &pcie4_intc 3>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 8>;
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status = "disabled";
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pcie4_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie5: pcie@5,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 62>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
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0x81000000 0 0 0x81000000 0x5 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie5_intc 0>,
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<0 0 0 2 &pcie5_intc 1>,
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<0 0 0 3 &pcie5_intc 2>,
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<0 0 0 4 &pcie5_intc 3>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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pcie5_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie6: pcie@6,0 {
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device_type = "pci";
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assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
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reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 63>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
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0x81000000 0 0 0x81000000 0x6 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie6_intc 0>,
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<0 0 0 2 &pcie6_intc 1>,
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<0 0 0 3 &pcie6_intc 2>,
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<0 0 0 4 &pcie6_intc 3>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 10>;
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status = "disabled";
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pcie6_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie7: pcie@7,0 {
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device_type = "pci";
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assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
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reg = <0x3800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 64>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
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0x81000000 0 0 0x81000000 0x7 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie7_intc 0>,
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<0 0 0 2 &pcie7_intc 1>,
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<0 0 0 3 &pcie7_intc 2>,
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<0 0 0 4 &pcie7_intc 3>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 11>;
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status = "disabled";
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pcie7_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie8: pcie@8,0 {
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device_type = "pci";
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assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
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reg = <0x4000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 65>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
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0x81000000 0 0 0x81000000 0x8 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie8_intc 0>,
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<0 0 0 2 &pcie8_intc 1>,
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<0 0 0 3 &pcie8_intc 2>,
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<0 0 0 4 &pcie8_intc 3>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 12>;
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status = "disabled";
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pcie8_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie9: pcie@9,0 {
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device_type = "pci";
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assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
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reg = <0x4800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 99>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
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0x81000000 0 0 0x81000000 0x9 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie9_intc 0>,
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<0 0 0 2 &pcie9_intc 1>,
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<0 0 0 3 &pcie9_intc 2>,
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<0 0 0 4 &pcie9_intc 3>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 26>;
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status = "disabled";
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pcie9_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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pcie10: pcie@a,0 {
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device_type = "pci";
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assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
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reg = <0x5000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&mpic 103>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
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0x81000000 0 0 0x81000000 0xa 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie10_intc 0>,
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<0 0 0 2 &pcie10_intc 1>,
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<0 0 0 3 &pcie10_intc 2>,
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<0 0 0 4 &pcie10_intc 3>;
|
|
marvell,pcie-port = <3>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 27>;
|
|
status = "disabled";
|
|
|
|
pcie10_intc: interrupt-controller {
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
internal-regs {
|
|
gpio0: gpio@18100 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
|
reg-names = "gpio", "pwm";
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <82>, <83>, <84>, <85>;
|
|
clocks = <&coreclk 0>;
|
|
};
|
|
|
|
gpio1: gpio@18140 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
|
reg-names = "gpio", "pwm";
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <87>, <88>, <89>, <90>;
|
|
clocks = <&coreclk 0>;
|
|
};
|
|
|
|
gpio2: gpio@18180 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18180 0x40>;
|
|
ngpios = <3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <91>;
|
|
};
|
|
|
|
eth3: ethernet@34000 {
|
|
compatible = "marvell,armada-xp-neta";
|
|
reg = <0x34000 0x4000>;
|
|
interrupts = <14>;
|
|
clocks = <&gateclk 1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
compatible = "marvell,mv78460-pinctrl";
|
|
};
|