mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
339 lines
8.6 KiB
Plaintext
339 lines
8.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Actions Semi S500 SoC
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*
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* Copyright (c) 2016-2017 Andreas Färber
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*/
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#include <dt-bindings/clock/actions,s500-cmu.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/owl-s500-powergate.h>
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#include <dt-bindings/reset/actions,s500-reset.h>
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/ {
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compatible = "actions,s500";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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};
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x0>;
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enable-method = "actions,s500-smp";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x1>;
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enable-method = "actions,s500-smp";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x2>;
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enable-method = "actions,s500-smp";
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power-domains = <&sps S500_PD_CPU2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x3>;
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enable-method = "actions,s500-smp";
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power-domains = <&sps S500_PD_CPU3>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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hosc: hosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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losc: losc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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scu: scu@b0020000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xb0020000 0x100>;
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};
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global_timer: timer@b0020200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xb0020200 0x100>;
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interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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twd_timer: timer@b0020600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xb0020600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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twd_wdt: wdt@b0020620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xb0020620 0xe0>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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gic: interrupt-controller@b0021000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0xb0021000 0x1000>,
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<0xb0020100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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l2: cache-controller@b0022000 {
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compatible = "arm,pl310-cache";
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reg = <0xb0022000 0x1000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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arm,tag-latency = <3 3 2>;
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arm,data-latency = <5 3 3>;
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};
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uart0: serial@b0120000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0120000 0x2000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART0>;
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status = "disabled";
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};
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uart1: serial@b0122000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0122000 0x2000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART1>;
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status = "disabled";
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};
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uart2: serial@b0124000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0124000 0x2000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART2>;
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status = "disabled";
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};
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uart3: serial@b0126000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0126000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART3>;
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status = "disabled";
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};
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uart4: serial@b0128000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0128000 0x2000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART4>;
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status = "disabled";
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};
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uart5: serial@b012a000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb012a000 0x2000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART5>;
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status = "disabled";
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};
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uart6: serial@b012c000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb012c000 0x2000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART6>;
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status = "disabled";
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};
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cmu: clock-controller@b0160000 {
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compatible = "actions,s500-cmu";
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reg = <0xb0160000 0x8000>;
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clocks = <&hosc>, <&losc>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2c0: i2c@b0170000 {
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compatible = "actions,s500-i2c";
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reg = <0xb0170000 0x4000>;
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clocks = <&cmu CLK_I2C0>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@b0174000 {
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compatible = "actions,s500-i2c";
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reg = <0xb0174000 0x4000>;
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clocks = <&cmu CLK_I2C1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@b0178000 {
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compatible = "actions,s500-i2c";
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reg = <0xb0178000 0x4000>;
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clocks = <&cmu CLK_I2C2>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@b017c000 {
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compatible = "actions,s500-i2c";
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reg = <0xb017c000 0x4000>;
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clocks = <&cmu CLK_I2C3>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sirq: interrupt-controller@b01b0200 {
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compatible = "actions,s500-sirq";
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reg = <0xb01b0200 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
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};
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timer: timer@b0168000 {
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compatible = "actions,s500-timer";
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reg = <0xb0168000 0x8000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
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};
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sps: power-controller@b01b0100 {
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compatible = "actions,s500-sps";
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reg = <0xb01b0100 0x100>;
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#power-domain-cells = <1>;
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};
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pinctrl: pinctrl@b01b0000 {
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compatible = "actions,s500-pinctrl";
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reg = <0xb01b0000 0x40>, /* GPIO */
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<0xb01b0040 0x10>, /* Multiplexing Control */
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<0xb01b0060 0x18>, /* PAD Control */
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<0xb01b0080 0xc>; /* PAD Drive Capacity */
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 132>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
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};
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dma: dma-controller@b0260000 {
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compatible = "actions,s500-dma";
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reg = <0xb0260000 0xd00>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <12>;
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dma-requests = <46>;
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clocks = <&cmu CLK_DMAC>;
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power-domains = <&sps S500_PD_DMA>;
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};
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mmc0: mmc@b0230000 {
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compatible = "actions,s500-mmc", "actions,owl-mmc";
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reg = <0xb0230000 0x38>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD0>;
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resets = <&cmu RESET_SD0>;
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dmas = <&dma 2>;
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dma-names = "mmc";
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status = "disabled";
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};
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mmc1: mmc@b0234000 {
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compatible = "actions,s500-mmc", "actions,owl-mmc";
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reg = <0xb0234000 0x38>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD1>;
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resets = <&cmu RESET_SD1>;
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dmas = <&dma 3>;
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dma-names = "mmc";
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status = "disabled";
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};
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mmc2: mmc@b0238000 {
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compatible = "actions,s500-mmc", "actions,owl-mmc";
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reg = <0xb0238000 0x38>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD2>;
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resets = <&cmu RESET_SD2>;
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dmas = <&dma 4>;
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dma-names = "mmc";
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status = "disabled";
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};
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ethernet: ethernet@b0310000 {
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compatible = "actions,s500-emac", "actions,owl-emac";
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reg = <0xb0310000 0x10000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>;
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clock-names = "eth", "rmii";
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resets = <&cmu RESET_ETHERNET>;
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status = "disabled";
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};
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};
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};
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