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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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179e949719
While the GCC and Clang compilers already define __ASSEMBLER__ automatically when compiling assembly code, __ASSEMBLY__ is a macro that only gets defined by the Makefiles in the kernel. This can be very confusing when switching between userspace and kernelspace coding, or when dealing with uapi headers that rather should use __ASSEMBLER__ instead. So let's standardize on the __ASSEMBLER__ macro that is provided by the compilers now. This is a completely mechanical patch (done with a simple "sed -i" statement). Cc: linux-snps-arc@lists.infradead.org Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
202 lines
4.3 KiB
C
202 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ASM_IRQFLAGS_ARCOMPACT_H
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#define __ASM_IRQFLAGS_ARCOMPACT_H
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/* vineetg: March 2010 : local_irq_save( ) optimisation
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* -Remove explicit mov of current status32 into reg, that is not needed
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* -Use BIC insn instead of INVERTED + AND
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* -Conditionally disable interrupts (if they are not enabled, don't disable)
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*/
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#include <asm/arcregs.h>
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/* status32 Reg bits related to Interrupt Handling */
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#define STATUS_E1_BIT 1 /* Int 1 enable */
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#define STATUS_E2_BIT 2 /* Int 2 enable */
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#define STATUS_A1_BIT 3 /* Int 1 active */
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#define STATUS_A2_BIT 4 /* Int 2 active */
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#define STATUS_AE_BIT 5 /* Exception active */
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#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
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#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
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#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
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#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
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#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
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#define STATUS_IE_MASK (STATUS_E1_MASK | STATUS_E2_MASK)
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/* Other Interrupt Handling related Aux regs */
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#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
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#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
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#define AUX_IRQ_LV12 0x43 /* interrupt level register */
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#define AUX_IENABLE 0x40c
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#define AUX_ITRIGGER 0x40d
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#define AUX_IPULSE 0x415
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#define ISA_INIT_STATUS_BITS STATUS_IE_MASK
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#ifndef __ASSEMBLER__
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/******************************************************************
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* IRQ Control Macros
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*
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* All of them have "memory" clobber (compiler barrier) which is needed to
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* ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
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* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
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*
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* Noted at the time of Abilis Timer List corruption
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*
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* Orig Bug + Rejected solution:
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* https://lore.kernel.org/lkml/1364553218-31255-1-git-send-email-vgupta@synopsys.com
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*
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* Reasoning:
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* https://lore.kernel.org/lkml/CA+55aFyFWjpSVQM6M266tKrG_ZXJzZ-nYejpmXYQXbrr42mGPQ@mail.gmail.com
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*
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******************************************************************/
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long temp, flags;
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__asm__ __volatile__(
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" lr %1, [status32] \n"
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" bic %0, %1, %2 \n"
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" and.f 0, %1, %2 \n"
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" flag.nz %0 \n"
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: "=r"(temp), "=r"(flags)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory", "cc");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(
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" flag %0 \n"
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:
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: "r"(flags)
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: "memory");
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}
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/*
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* Unconditionally Enable IRQs
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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extern void arch_local_irq_enable(void);
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#else
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static inline void arch_local_irq_enable(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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" or %0, %0, %1 \n"
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" flag %0 \n"
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: "=&r"(temp)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "cc", "memory");
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}
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#endif
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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" and %0, %0, %1 \n"
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" flag %0 \n"
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: "=&r"(temp)
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: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory");
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp)
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:
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: "memory");
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_E1_MASK
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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| STATUS_E2_MASK
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#endif
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));
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#else
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#ifdef CONFIG_TRACE_IRQFLAGS
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.macro TRACE_ASM_IRQ_DISABLE
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bl trace_hardirqs_off
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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bl trace_hardirqs_on
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.endm
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#else
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.macro TRACE_ASM_IRQ_DISABLE
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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.endm
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#endif
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.macro IRQ_DISABLE scratch
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lr \scratch, [status32]
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bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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TRACE_ASM_IRQ_DISABLE
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.endm
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.macro IRQ_ENABLE scratch
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TRACE_ASM_IRQ_ENABLE
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lr \scratch, [status32]
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or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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.endm
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#endif /* __ASSEMBLER__ */
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#endif
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