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6d7965fb5c
The Synopsys DWC3 core is found either as a standalone block or integrated with vendor glue logic. So far the latter has been described as two separate IP blocks in DeviceTree, but the two parts are not separate. In the case where the core is integrated together with vendor glue, resources such as clock and resets are often customized by the vendor, such that the standard properties doesn't make sense. Split the snps,dwc3 binding in a description of the core properties and the standard "glue" properties, in order to allow vendor bindings to inherit the core properties. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250113-dwc3-refactor-v3-1-d1722075df7b@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
107 lines
2.5 KiB
YAML
107 lines
2.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare USB3 Controller
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maintainers:
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- Felipe Balbi <balbi@kernel.org>
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description:
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This is usually a subnode to DWC3 glue to which it is connected, but can also
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be presented as a standalone DT node with an optional vendor-specific
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compatible string.
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allOf:
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- $ref: snps,dwc3-common.yaml#
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properties:
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compatible:
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contains:
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oneOf:
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- const: snps,dwc3
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- const: synopsys,dwc3
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deprecated: true
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reg:
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maxItems: 1
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interrupts:
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description:
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It's either a single common DWC3 interrupt (dwc_usb3) or individual
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interrupts for the host, gadget and DRD modes.
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minItems: 1
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maxItems: 4
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interrupt-names:
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minItems: 1
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maxItems: 4
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oneOf:
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- const: dwc_usb3
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- items:
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enum: [host, peripheral, otg, wakeup]
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clocks:
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description:
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In general the core supports three types of clocks. bus_early is a
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SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
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PHY is suspended. suspend clocks a small part of the USB3 core when
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SS PHY in P3. But particular cases may differ from that having less
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or more clock sources with another names.
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clock-names:
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contains:
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anyOf:
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- enum: [bus_early, ref, suspend]
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- true
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dma-coherent: true
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iommus:
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maxItems: 1
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power-domains:
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description:
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The DWC3 has 2 power-domains. The power management unit (PMU) and
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everything else. The PMU is typically always powered and may not have an
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entry.
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minItems: 1
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items:
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- description: Core
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- description: Power management unit
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resets:
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minItems: 1
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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examples:
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- |
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usb@4a030000 {
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compatible = "snps,dwc3";
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reg = <0x4a030000 0xcfff>;
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interrupts = <0 92 4>;
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usb-phy = <&usb2_phy>, <&usb3_phy>;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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};
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- |
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usb@4a000000 {
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compatible = "snps,dwc3";
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reg = <0x4a000000 0xcfff>;
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interrupts = <0 92 4>;
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clocks = <&clk 1>, <&clk 2>, <&clk 3>;
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clock-names = "bus_early", "ref", "suspend";
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phys = <&usb2_phy>, <&usb3_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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};
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...
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