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6d1ca2236d
Add compatible string for ESWIN EIC7700 CLINT. Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250410152519.1358964-9-pinkesh.vaghela@einfochips.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
106 lines
3.3 KiB
YAML
106 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive Core Local Interruptor
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maintainers:
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- Palmer Dabbelt <palmer@dabbelt.com>
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- Anup Patel <anup.patel@wdc.com>
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description:
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SiFive (and other RISC-V) SOCs include an implementation of the SiFive
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Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
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interrupts. It directly connects to the timer and inter-processor interrupt
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lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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interrupt controller is the parent interrupt controller for CLINT device.
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The clock frequency of CLINT is specified via "timebase-frequency" DT
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property of "/cpus" DT node. The "timebase-frequency" DT property is
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described in Documentation/devicetree/bindings/riscv/cpus.yaml
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T-Head C906/C910 CPU cores include an implementation of CLINT too, however
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their implementation lacks a memory-mapped MTIME register, thus not
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compatible with SiFive ones.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- canaan,k210-clint # Canaan Kendryte K210
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- eswin,eic7700-clint # ESWIN EIC7700
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- sifive,fu540-c000-clint # SiFive FU540
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- spacemit,k1-clint # SpacemiT K1
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- starfive,jh7100-clint # StarFive JH7100
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- starfive,jh7110-clint # StarFive JH7110
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- starfive,jh8100-clint # StarFive JH8100
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- const: sifive,clint0 # SiFive CLINT v0 IP block
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- items:
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- {}
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- const: sifive,clint2 # SiFive CLINT v2 IP block
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description:
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SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
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differs from that of sifive,clint0, making them incompatible.
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- items:
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- enum:
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- allwinner,sun20i-d1-clint
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- sophgo,cv1800b-clint
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- sophgo,cv1812h-clint
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- sophgo,sg2002-clint
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- thead,th1520-clint
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- const: thead,c900-clint
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- items:
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- const: sifive,clint0
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- const: riscv,clint0
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deprecated: true
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description: For the QEMU virt machine only
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description:
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Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
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when compatible with a SiFive CLINT. Please refer to
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sifive-blocks-ip-versioning.txt for details regarding the latter.
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 4095
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sifive,fine-ctr-bits:
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maximum: 15
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description: The width in bits of the fine counter.
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if:
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properties:
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compatible:
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contains:
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const: sifive,clint2
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then:
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required:
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- sifive,fine-ctr-bits
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else:
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properties:
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sifive,fine-ctr-bits: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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timer@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
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<&cpu2intc 3>, <&cpu2intc 7>,
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<&cpu3intc 3>, <&cpu3intc 7>,
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<&cpu4intc 3>, <&cpu4intc 7>;
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reg = <0x2000000 0x10000>;
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};
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...
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