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65bbf10b93
Add the DT binding documentation for Andes machine timer. The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Andes machiner timer (PLMT0) is the implementation of the machine timer, and it contains memory-mapped registers (mtime and mtimecmp). This device supports up to 32 cores. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-6-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
54 lines
1.4 KiB
YAML
54 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes machine-level timer
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description:
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The Andes machine-level timer device (PLMT0) provides machine-level timer
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functionality for a set of HARTs on a RISC-V platform. It has a single
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fixed-frequency monotonic time counter (MTIME) register and a time compare
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register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
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generated if MTIME >= MTIMECMP.
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maintainers:
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- Ben Zong-You Xie <ben717@andestech.com>
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properties:
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compatible:
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items:
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- enum:
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- andestech,qilai-plmt
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- const: andestech,plmt0
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 32
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description:
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Specifies which harts are connected to the PLMT0. Each item must points
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to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
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PLMT0 supports 1 hart up to 32 harts.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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interrupt-controller@100000 {
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compatible = "andestech,qilai-plmt", "andestech,plmt0";
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reg = <0x100000 0x100000>;
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interrupts-extended = <&cpu0intc 7>,
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<&cpu1intc 7>,
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<&cpu2intc 7>,
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<&cpu3intc 7>;
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};
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