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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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44b91d61c5
Add dt-bindings for the RSPI IP found inside the Renesas RZ/V2H(P) SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250704162036.468765-2-fabrizio.castro.jz@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
97 lines
2.2 KiB
YAML
97 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/renesas,rzv2h-rspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI)
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maintainers:
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- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: renesas,r9a09g057-rspi # RZ/V2H(P)
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Idle Interrupt
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- description: Error Interrupt
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- description: Communication End Interrupt
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- description: Receive Buffer Full Interrupt
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- description: Transmit Buffer Empty Interrupt
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interrupt-names:
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items:
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- const: idle
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- const: error
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- const: end
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- const: rx
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- const: tx
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pclk
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- const: pclk_sfr
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- const: tclk
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: presetn
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- const: tresetn
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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spi@12800800 {
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compatible = "renesas,r9a09g057-rspi";
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reg = <0x12800800 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "idle", "error", "end", "rx", "tx";
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clocks = <&cpg CPG_MOD 0x5a>,
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<&cpg CPG_MOD 0x5b>,
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<&cpg CPG_MOD 0x5c>;
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clock-names = "pclk", "pclk_sfr", "tclk";
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resets = <&cpg 0x7f>, <&cpg 0x80>;
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reset-names = "presetn", "tresetn";
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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