mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
4614fd6342
Add the 'iommus' property to the Tegra QSPI device tree binding. The property is needed for Tegra234 when using the internal DMA controller, and is not supported on other Tegra chips, as DMA is handled by an external controller. Signed-off-by: Vishwaroop A <va@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20250513200043.608292-1-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
112 lines
2.2 KiB
YAML
112 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Quad SPI Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra210-qspi
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- nvidia,tegra186-qspi
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- nvidia,tegra194-qspi
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- nvidia,tegra234-qspi
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- nvidia,tegra241-qspi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: qspi
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- const: qspi_out
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clocks:
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maxItems: 2
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resets:
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maxItems: 1
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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iommus:
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maxItems: 1
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patternProperties:
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"@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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spi-rx-bus-width:
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enum: [1, 2, 4]
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spi-tx-bus-width:
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enum: [1, 2, 4]
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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- resets
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unevaluatedProperties: false
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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not:
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contains:
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const: nvidia,tegra234-qspi
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then:
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properties:
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iommus: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/reset/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@70410000 {
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compatible = "nvidia,tegra210-qspi";
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reg = <0x70410000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA210_CLK_QSPI>,
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<&tegra_car TEGRA210_CLK_QSPI_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&tegra_car 211>;
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dmas = <&apbdma 5>, <&apbdma 5>;
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dma-names = "rx", "tx";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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nvidia,tx-clk-tap-delay = <0>;
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nvidia,rx-clk-tap-delay = <0>;
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};
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};
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