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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9e699b8985
Add DT binding schema for components belonging to the platform-specific AHCI glue layer implemented in UniPhier SoCs. This AHCI glue layer works as a sideband logic for the host controller, including core reset, PHYs, and some signals to the controller. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221213082449.2721-18-hayashi.kunihiko@socionext.com Signed-off-by: Rob Herring <robh@kernel.org>
78 lines
1.9 KiB
YAML
78 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier SoC AHCI glue layer
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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description: |+
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AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
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logic handling signals to AHCI host controller inside AHCI component.
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properties:
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compatible:
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items:
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- enum:
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- socionext,uniphier-pro4-ahci-glue
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- socionext,uniphier-pxs2-ahci-glue
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- socionext,uniphier-pxs3-ahci-glue
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- const: simple-mfd
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^reset-controller@[0-9a-f]+$":
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$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
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"phy@[0-9a-f]+$":
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$ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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sata-controller@65700000 {
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compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
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reg = <0x65b00000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65700000 0x100>;
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reset-controller@0 {
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compatible = "socionext,uniphier-pxs3-ahci-reset";
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reg = <0x0 0x4>;
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clock-names = "link";
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clocks = <&sys_clk 28>;
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reset-names = "link";
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resets = <&sys_rst 28>;
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#reset-cells = <1>;
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};
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phy@10 {
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compatible = "socionext,uniphier-pxs3-ahci-phy";
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reg = <0x10 0x10>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 28>, <&sys_clk 30>;
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reset-names = "link", "phy";
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resets = <&sys_rst 28>, <&sys_rst 30>;
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#phy-cells = <0>;
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};
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};
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