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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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fd4a06a2e1
Document support for the USB2PHY reset controller found on the Renesas RZ/V2N (R9A09G056) SoC. The reset controller IP is functionally identical to that on the RZ/V2H(P) SoC, so no driver changes are needed. The existing `renesas,r9a09g057-usb2phy-reset` compatible will be used as a fallback for the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250528133031.167647-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
62 lines
1.2 KiB
YAML
62 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) USB2PHY Port reset Control
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the
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USB2.0 PHY.
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properties:
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compatible:
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oneOf:
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- items:
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- const: renesas,r9a09g056-usb2phy-reset # RZ/V2N
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- const: renesas,r9a09g057-usb2phy-reset
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- const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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'#reset-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- resets
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- power-domains
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
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reset-controller@15830000 {
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compatible = "renesas,r9a09g057-usb2phy-reset";
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reg = <0x15830000 0x10000>;
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clocks = <&cpg CPG_MOD 0xb6>;
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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};
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